Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23321

1

T1

20

T2

3

T4

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

17727

1

T1

20

T2

3

T4

13

auto[ADC_CTRL_FILTER_COND_OUT]

5594

1

T11

6

T14

13

T15

4

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17586

1

T1

20

T2

3

T4

13

auto[1]

5735

1

T11

6

T16

1

T17

17

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19493

1

T1

20

T2

3

T4

13

auto[1]

3828

1

T12

1

T13

13

T15

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	74	1			T53	17		T118	13		T287	23
values[0]	10	1			T163	2		T288	1		T214	3
values[1]	638	1			T52	4		T66	26		T95	23
values[2]	875	1			T14	13		T18	21		T222	9
values[3]	426	1			T20	3		T87	8		T53	14
values[4]	563	1			T38	13		T135	2		T128	1
values[5]	698	1			T12	2		T93	6		T126	3
values[6]	535	1			T42	3		T66	6		T120	1
values[7]	521	1			T87	5		T58	1		T95	23
values[8]	760	1			T13	9		T15	4		T91	23
values[9]	3645	1			T11	6		T16	1		T17	17
minimum	14576	1			T1	20		T2	3		T4	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	881	1			T52	4		T95	23		T38	9
values[1]	3047	1			T14	13		T16	1		T17	17
values[2]	548	1			T20	3		T87	8		T53	14
values[3]	642	1			T93	6		T38	13		T126	3
values[4]	487	1			T12	2		T135	1		T120	1
values[5]	535	1			T42	3		T66	6		T120	1
values[6]	666	1			T13	9		T87	5		T58	1
values[7]	753	1			T15	4		T40	33		T135	1
values[8]	947	1			T11	6		T20	3		T117	8
values[9]	239	1			T118	13		T121	10		T49	1
minimum	14576	1			T1	20		T2	3		T4	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19298

1

T1

20

T2

3

T4

13

auto[1]

4023

1

T11

1

T14

12

T15

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T52	4		T44	3		T150	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T95	11		T38	3		T119	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T18	11		T66	14		T131	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1531	1			T14	13		T16	1		T17	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T87	1		T53	14		T222	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T20	2		T93	8		T142	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T135	1		T130	1		T132	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T93	1		T38	8		T126	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T12	1		T120	1		T136	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T135	1		T177	10		T183	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T220	1		T128	8		T131	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T42	3		T66	2		T120	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T13	1		T91	10		T95	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T87	1		T58	1		T119	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T135	1		T120	1		T127	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T15	3		T40	15		T46	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T20	2		T117	1		T53	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	375	1			T11	6		T43	2		T45	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T49	1		T265	8		T60	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T118	13		T121	1		T269	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14491	1			T1	20		T2	3		T4	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T44	1		T150	16		T133	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T95	12		T38	6		T215	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T18	10		T66	12		T131	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1008	1			T17	15		T41	8		T88	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T87	7		T239	1		T139	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T20	1		T93	6		T142	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T132	9		T138	10		T240	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T93	5		T38	5		T126	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T12	1		T183	3		T169	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T177	9		T183	12		T89	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T131	5		T289	5		T256	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T66	4		T121	7		T132	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T13	8		T91	13		T95	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T87	4		T130	10		T228	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T132	15		T219	9		T252	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T15	1		T40	18		T130	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T20	1		T117	7		T251	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T231	3		T133	11		T169	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T278	1		T290	14		T291	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T121	9		T256	13		T258	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T13	5		T15	3		T38	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T53	17		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T118	13		T287	12		T292	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T163	2		T214	3		T293	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T288	1		T294	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T52	4		T66	14		T44	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T95	11		T38	3		T149	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T18	11		T222	9		T150	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T14	13		T119	1		T221	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T87	1		T53	14		T167	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T20	2		T93	8		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T135	1		T130	1		T183	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T38	8		T135	1		T128	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T12	1		T136	1		T220	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T93	1		T126	1		T183	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T120	1		T128	8		T169	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T42	3		T66	2		T121	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T95	11		T136	1		T219	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T87	1		T58	1		T119	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T13	1		T91	10		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T15	3		T216	4		T46	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T20	2		T117	1		T48	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1966	1			T11	6		T16	1		T17	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14491	1			T1	20		T2	3		T4	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T287	11		T292	13		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T66	12		T44	1		T133	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T95	12		T38	6		T219	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T18	10		T150	16		T131	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T221	12		T215	10		T133	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T87	7		T240	9		T239	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T20	1		T93	6		T142	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T183	3		T138	10		T223	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T38	5		T177	9		T142	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T12	1		T131	5		T132	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T93	5		T126	2		T183	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T169	18		T256	6		T253	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T66	4		T121	7		T132	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T95	12		T219	12		T289	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T87	4		T130	10		T209	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T13	8		T91	13		T177	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T15	1		T130	13		T239	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T20	1		T117	7		T132	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1197	1			T17	15		T40	18		T41	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T13	5		T15	3		T38	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T52	1		T44	4		T150	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T95	13		T38	7		T119	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T18	11		T66	13		T131	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1336	1			T14	1		T16	1		T17	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T87	8		T53	1		T222	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T20	3		T93	7		T142	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T135	1		T130	1		T132	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T93	6		T38	6		T126	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T12	2		T120	1		T136	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T135	1		T177	10		T183	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T220	1		T128	1		T131	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T42	3		T66	5		T120	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T13	9		T91	14		T95	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T87	5		T58	1		T119	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T135	1		T120	1		T127	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T15	3		T40	19		T46	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T20	2		T117	8		T53	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T11	5		T43	2		T45	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T49	1		T265	1		T60	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T118	1		T121	10		T269	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14576	1			T1	20		T2	3		T4	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T52	3		T150	16		T122	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T95	10		T38	2		T215	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T18	10		T66	13		T169	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1203	1			T14	12		T19	25		T243	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T53	13		T222	8		T167	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T93	7		T224	14		T295	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T132	8		T138	9		T240	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T38	7		T138	15		T276	23
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T183	6		T169	15		T296	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T177	9		T183	12		T144	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T128	7		T242	14		T253	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T66	1		T132	14		T283	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T91	9		T95	10		T177	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T216	3		T228	13		T239	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T127	1		T132	11		T167	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T15	1		T40	14		T228	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T20	1		T53	16		T245	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T11	1		T231	8		T169	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T265	7		T290	15		T291	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T118	12		T269	17		T258	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T53	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T118	1		T287	12		T292	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T163	2		T214	1		T293	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T288	1		T294	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T52	1		T66	13		T44	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T95	13		T38	7		T149	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T18	11		T222	1		T150	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T14	1		T119	1		T221	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T87	8		T53	1		T167	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T20	3		T93	7		T142	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T135	1		T130	1		T183	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T38	6		T135	1		T128	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T12	2		T136	1		T220	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T93	6		T126	3		T183	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T120	1		T128	1		T169	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T42	3		T66	5		T121	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T95	13		T136	1		T219	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T87	5		T58	1		T119	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T13	9		T91	14		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T15	3		T216	1		T46	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T20	2		T117	8		T48	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1589	1			T11	5		T16	1		T17	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14576	1			T1	20		T2	3		T4	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T53	16		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T118	12		T287	11		T292	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T214	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T52	3		T66	13		T122	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T95	10		T38	2		T122	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T18	10		T222	8		T150	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T14	12		T215	10		T138	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T53	13		T167	7		T240	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T93	7		T271	14		T277	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T183	6		T138	9		T233	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T38	7		T177	9		T276	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T132	8		T240	10		T266	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T183	12		T138	15		T297	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T128	7		T169	15		T242	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T66	1		T132	14		T144	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T95	10		T219	12		T245	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T214	11		T209	9		T250	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T91	9		T127	1		T177	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T15	1		T216	3		T239	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T20	1		T132	11		T245	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1574	1			T11	1		T19	25		T40	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19298

1

T1

20

T2

3

T4

13

auto[1]

auto[0]

4023

1

T11

1

T14

12

T15

1