Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23321

1

T1

20

T2

3

T4

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19770

1

T1

20

T2

3

T4

13

auto[ADC_CTRL_FILTER_COND_OUT]

3551

1

T11

6

T13

9

T15

4

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17389

1

T1

20

T2

3

T4

13

auto[1]

5932

1

T11

6

T14

13

T16

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19493

1

T1

20

T2

3

T4

13

auto[1]

3828

1

T12

1

T13

13

T15

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	14	1			T298	14		-	-		-	-
values[0]	57	1			T128	1		T246	14		T299	6
values[1]	675	1			T12	2		T15	4		T95	23
values[2]	754	1			T11	6		T93	6		T95	23
values[3]	579	1			T14	13		T52	4		T66	6
values[4]	539	1			T18	21		T87	8		T42	3
values[5]	584	1			T91	23		T131	6		T133	3
values[6]	723	1			T53	14		T122	3		T48	3
values[7]	676	1			T20	3		T87	5		T53	17
values[8]	709	1			T20	3		T43	2		T126	3
values[9]	3435	1			T13	9		T16	1		T17	17
minimum	14576	1			T1	20		T2	3		T4	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	988	1			T12	2		T15	4		T95	23
values[1]	754	1			T11	6		T14	13		T52	4
values[2]	469	1			T18	21		T93	6		T66	6
values[3]	524	1			T87	8		T42	3		T222	9
values[4]	695	1			T91	23		T131	6		T133	3
values[5]	643	1			T20	3		T53	31		T122	3
values[6]	2980	1			T16	1		T17	17		T19	28
values[7]	621	1			T126	3		T150	33		T136	1
values[8]	941	1			T13	9		T40	33		T117	8
values[9]	111	1			T119	1		T131	4		T163	2
minimum	14595	1			T1	20		T2	3		T4	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19298

1

T1

20

T2

3

T4

13

auto[1]

4023

1

T11

1

T14

12

T15

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T12	1		T38	3		T221	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T15	3		T95	11		T121	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T14	13		T52	4		T129	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T11	6		T95	11		T120	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T18	11		T93	1		T149	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T66	2		T220	1		T133	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T222	9		T119	1		T128	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T87	1		T42	3		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T91	10		T131	1		T156	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T133	1		T251	9		T300	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T53	14		T251	1		T244	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T20	2		T53	17		T122	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1606	1			T16	1		T17	2		T19	28
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T20	2		T58	1		T120	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T126	1		T150	17		T136	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T45	2		T215	11		T132	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T40	15		T66	14		T43	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T13	1		T117	1		T93	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T119	1		T256	1		T218	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T131	1		T163	2		T223	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14508	1			T1	20		T2	3		T4	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T12	1		T38	6		T221	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T15	1		T95	12		T121	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T183	3		T142	13		T219	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T95	12		T133	11		T169	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T18	10		T93	5		T121	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T66	4		T133	11		T89	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T177	3		T169	14		T219	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T87	7		T240	9		T232	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T91	13		T131	5		T239	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T133	2		T251	10		T255	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T251	1		T244	12		T39	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T20	1		T130	23		T183	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1036	1			T17	15		T41	8		T87	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T20	1		T132	15		T252	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T126	2		T150	16		T142	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T215	9		T132	9		T138	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T40	18		T66	12		T44	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T13	8		T117	7		T93	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T256	4		T218	1		T254	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T131	3		T223	13		T260	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T13	5		T15	3		T38	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T298	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T246	14		T171	1		T301	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T128	1		T299	1		T302	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T12	1		T38	3		T221	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T15	3		T95	11		T121	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T93	1		T216	4		T121	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T11	6		T95	11		T120	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T14	13		T52	4		T149	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T66	2		T220	1		T133	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T18	11		T222	9		T119	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T87	1		T42	3		T135	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T91	10		T131	1		T169	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T133	1		T240	13		T300	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T53	14		T251	1		T244	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T122	3		T48	3		T130	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T87	1		T38	8		T136	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T20	2		T53	17		T58	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T43	2		T126	1		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T20	2		T45	2		T215	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1725	1			T16	1		T17	2		T19	28
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T13	1		T117	1		T93	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14491	1			T1	20		T2	3		T4	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T298	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T171	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T299	5		T303	1		T298	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T12	1		T38	6		T221	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T15	1		T95	12		T121	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T93	5		T121	7		T215	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T95	12		T169	11		T212	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T183	3		T138	12		T276	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T66	4		T133	22		T89	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T18	10		T177	3		T219	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T87	7		T289	5		T232	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T91	13		T131	5		T169	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T133	2		T240	9		T276	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T251	1		T244	12		T39	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T130	10		T183	12		T132	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T87	4		T38	5		T169	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T20	1		T130	13		T252	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T126	2		T142	8		T131	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T20	1		T215	9		T132	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1117	1			T17	15		T40	18		T41	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T13	8		T117	7		T93	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T13	5		T15	3		T38	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T12	2		T38	7		T221	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T15	3		T95	13		T121	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T14	1		T52	1		T129	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T11	5		T95	13		T120	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T18	11		T93	6		T149	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T66	5		T220	1		T133	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T222	1		T119	1		T128	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T87	8		T42	3		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T91	14		T131	6		T156	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T133	3		T251	11		T300	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T53	1		T251	2		T244	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T20	2		T53	1		T122	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1374	1			T16	1		T17	17		T19	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T20	3		T58	1		T120	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T126	3		T150	17		T136	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T45	2		T215	10		T132	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T40	19		T66	13		T43	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T13	9		T117	8		T93	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T119	1		T256	5		T218	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T131	4		T163	2		T223	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14581	1			T1	20		T2	3		T4	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T38	2		T226	13		T138	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T15	1		T95	10		T122	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T14	12		T52	3		T183	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T11	1		T95	10		T167	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T18	10		T216	3		T144	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T66	1		T89	1		T245	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T222	8		T128	7		T177	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T240	12		T245	15		T276	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T91	9		T239	10		T242	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T251	8		T146	2		T159	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T53	13		T244	12		T266	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T20	1		T53	16		T122	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1268	1			T19	25		T38	7		T243	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T132	11		T252	19		T232	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T150	16		T132	14		T140	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T215	10		T132	8		T138	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T40	14		T66	13		T118	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T93	7		T262	8		T240	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T254	19		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T304	13		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T305	12		T306	2		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T298	5		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T246	1		T171	12		T301	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T128	1		T299	6		T302	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T12	2		T38	7		T221	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T15	3		T95	13		T121	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T93	6		T216	1		T121	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T11	5		T95	13		T120	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T14	1		T52	1		T149	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T66	5		T220	1		T133	24
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T18	11		T222	1		T119	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T87	8		T42	3		T135	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T91	14		T131	6		T169	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T133	3		T240	10		T300	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T53	1		T251	2		T244	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T122	1		T48	3		T130	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T87	5		T38	6		T136	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T20	2		T53	1		T58	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T43	2		T126	3		T142	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T20	3		T45	2		T215	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1481	1			T16	1		T17	17		T19	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	343	1			T13	9		T117	8		T93	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14576	1			T1	20		T2	3		T4	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T298	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T246	13		T301	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T303	1		T298	6		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T38	2		T138	9		T185	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T15	1		T95	10		T122	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T216	3		T219	3		T226	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T11	1		T95	10		T167	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T14	12		T52	3		T183	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T66	1		T89	1		T245	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T18	10		T222	8		T128	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T245	15		T307	7		T308	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T91	9		T169	13		T239	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T240	12		T276	13		T296	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T53	13		T244	12		T242	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T122	2		T183	12		T132	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T38	7		T169	15		T266	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T20	1		T53	16		T127	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T132	14		T140	11		T146	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T215	10		T132	8		T252	21
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1361	1			T19	25		T40	14		T66	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T93	7		T138	6		T262	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19298

1

T1

20

T2

3

T4

13

auto[1]

auto[0]

4023

1

T11

1

T14

12

T15

1