Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23321

1

T1

20

T2

3

T4

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19940

1

T1

20

T2

3

T4

13

auto[ADC_CTRL_FILTER_COND_OUT]

3381

1

T14

13

T18

21

T20

6

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17490

1

T1

20

T2

3

T4

13

auto[1]

5831

1

T13

9

T14

13

T15

4

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19493

1

T1

20

T2

3

T4

13

auto[1]

3828

1

T12

1

T13

13

T15

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	187	1			T95	23		T48	3		T219	25
values[0]	1	1			T273	1		-	-		-	-
values[1]	739	1			T38	9		T120	1		T121	8
values[2]	2886	1			T16	1		T17	17		T19	28
values[3]	615	1			T20	3		T40	33		T93	14
values[4]	585	1			T11	6		T38	13		T222	9
values[5]	626	1			T87	8		T93	6		T66	6
values[6]	643	1			T15	4		T53	17		T58	1
values[7]	679	1			T150	33		T136	1		T231	12
values[8]	695	1			T12	2		T13	9		T18	21
values[9]	1089	1			T14	13		T117	8		T52	4
minimum	14576	1			T1	20		T2	3		T4	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	890	1			T38	9		T43	2		T120	1
values[1]	2700	1			T16	1		T17	17		T19	28
values[2]	582	1			T40	33		T93	14		T222	9
values[3]	718	1			T11	6		T87	8		T38	13
values[4]	548	1			T93	6		T66	6		T118	13
values[5]	702	1			T15	4		T53	17		T58	1
values[6]	668	1			T12	2		T13	9		T42	3
values[7]	734	1			T18	21		T20	3		T53	14
values[8]	974	1			T14	13		T117	8		T52	4
values[9]	60	1			T135	1		T184	1		T274	1
minimum	14745	1			T1	20		T2	3		T4	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19298

1

T1

20

T2

3

T4

13

auto[1]

4023

1

T11

1

T14

12

T15

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T38	3		T215	11		T128	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T43	2		T120	1		T221	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1512	1			T16	1		T17	2		T19	28
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T20	2		T87	1		T136	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T122	3		T130	1		T132	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T40	15		T93	8		T222	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T11	6		T87	1		T38	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T126	1		T120	1		T215	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T66	2		T142	1		T156	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T93	1		T118	13		T120	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T15	3		T167	8		T144	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T53	17		T58	1		T44	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T12	1		T13	1		T42	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T119	1		T150	17		T136	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T149	1		T127	2		T227	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T18	11		T20	2		T53	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T117	1		T52	4		T95	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T14	13		T91	10		T66	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T274	1		T275	1		T299	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T135	1		T184	1		T230	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14536	1			T1	20		T2	3		T4	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T237	1		T289	1		T309	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T38	6		T215	9		T138	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T221	12		T169	14		T238	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	950	1			T17	15		T41	8		T88	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T20	1		T87	4		T139	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T132	9		T230	3		T278	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T40	18		T93	6		T130	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T87	7		T38	5		T142	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T126	2		T215	1		T131	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T66	4		T142	8		T279	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T93	5		T219	1		T239	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T15	1		T239	1		T241	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T44	1		T231	3		T132	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T12	1		T13	8		T133	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T150	16		T183	3		T219	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T227	10		T229	12		T297	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T18	10		T20	1		T121	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T117	7		T95	12		T131	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T91	13		T66	12		T95	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T299	5		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T230	5		T263	14		T310	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T13	5		T15	3		T38	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T289	5		T309	2		T277	8

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T95	11		T274	1		T213	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T48	3		T219	13		T184	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T273	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T38	3		T121	1		T177	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T120	1		T221	1		T122	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1573	1			T16	1		T17	2		T19	28
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T87	1		T43	2		T136	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T119	1		T129	1		T177	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T20	2		T40	15		T93	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T11	6		T38	8		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T222	9		T126	1		T130	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T87	1		T66	2		T142	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T93	1		T120	2		T215	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T15	3		T42	3		T167	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T53	17		T58	1		T118	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T133	1		T144	7		T245	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T150	17		T136	1		T231	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T12	1		T13	1		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T18	11		T20	2		T53	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	307	1			T117	1		T52	4		T149	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T14	13		T91	10		T66	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14491	1			T1	20		T2	3		T4	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T95	12		T230	4		T255	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T219	12		T185	5		T263	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T38	6		T121	7		T177	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T221	12		T169	14		T238	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1036	1			T17	15		T41	8		T88	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T87	4		T251	10		T185	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T177	9		T230	3		T157	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T20	1		T40	18		T93	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T38	5		T142	13		T132	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T126	2		T130	10		T133	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T87	7		T66	4		T142	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T93	5		T215	1		T131	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T15	1		T239	1		T282	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T44	1		T169	18		T219	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T133	2		T228	1		T241	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T150	16		T231	3		T183	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T12	1		T13	8		T229	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T18	10		T20	1		T121	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T117	7		T131	3		T132	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T91	13		T66	12		T95	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T13	5		T15	3		T38	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T38	7		T215	10		T128	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T43	2		T120	1		T221	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1286	1			T16	1		T17	17		T19	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T20	2		T87	5		T136	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T122	1		T130	1		T132	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T40	19		T93	7		T222	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T11	5		T87	8		T38	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T126	3		T120	1		T215	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T66	5		T142	9		T156	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T93	6		T118	1		T120	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T15	3		T167	1		T144	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T53	1		T58	1		T44	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T12	2		T13	9		T42	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T119	1		T150	17		T136	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T149	1		T127	1		T227	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T18	11		T20	3		T53	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T117	8		T52	1		T95	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T14	1		T91	14		T66	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T274	1		T275	1		T299	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T135	1		T184	1		T230	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14641	1			T1	20		T2	3		T4	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T237	1		T289	6		T309	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T38	2		T215	10		T128	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T122	16		T169	13		T251	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1176	1			T19	25		T243	8		T154	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T20	1		T250	4		T287	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T122	2		T132	8		T242	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T40	14		T93	7		T222	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T11	1		T38	7		T216	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T266	12		T214	2		T246	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T66	1		T279	13		T170	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T118	12		T239	13		T224	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T15	1		T167	7		T144	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T53	16		T231	8		T132	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T144	6		T228	13		T233	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T150	16		T183	6		T219	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T127	1		T227	9		T229	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T18	10		T53	13		T240	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T52	3		T95	10		T132	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T14	12		T91	9		T66	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T263	15		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T177	10		T228	12		T311	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T277	11		T284	12		T312	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T95	13		T274	1		T213	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T48	3		T219	13		T184	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T273	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T38	7		T121	8		T177	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T120	1		T221	13		T122	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1375	1			T16	1		T17	17		T19	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T87	5		T43	2		T136	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T119	1		T129	1		T177	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T20	2		T40	19		T93	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T11	5		T38	6		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T222	1		T126	3		T130	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T87	8		T66	5		T142	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T93	6		T120	2		T215	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T15	3		T42	3		T167	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T53	1		T58	1		T118	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T133	3		T144	1		T245	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T150	17		T136	1		T231	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T12	2		T13	9		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T18	11		T20	3		T53	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T117	8		T52	1		T149	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T14	1		T91	14		T66	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14576	1			T1	20		T2	3		T4	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T95	10		T265	13		T236	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T219	12		T185	6		T263	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T38	2		T177	10		T138	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T122	16		T169	13		T209	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1234	1			T19	25		T243	8		T154	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T251	8		T185	18		T250	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T177	9		T242	14		T286	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T20	1		T40	14		T93	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T11	1		T38	7		T216	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T222	8		T266	12		T246	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T66	1		T140	11		T279	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T239	13		T214	2		T224	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T15	1		T167	7		T144	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T53	16		T118	12		T169	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T144	6		T245	14		T228	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T150	16		T231	8		T183	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T127	1		T229	20		T313	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T18	10		T53	13		T262	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T52	3		T132	11		T138	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T14	12		T91	9		T66	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19298

1

T1

20

T2

3

T4

13

auto[1]

auto[0]

4023

1

T11

1

T14

12

T15

1