Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23321

1

T1

20

T2

3

T4

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20424

1

T1

20

T2

3

T4

13

auto[ADC_CTRL_FILTER_COND_OUT]

2897

1

T12

2

T13

9

T14

13

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17488

1

T1

20

T2

3

T4

13

auto[1]

5833

1

T11

6

T12

2

T13

9

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19493

1

T1

20

T2

3

T4

13

auto[1]

3828

1

T12

1

T13

13

T15

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	35	1			T183	10		T219	13		T272	1
values[0]	85	1			T87	8		T131	10		T39	5
values[1]	402	1			T53	17		T121	10		T237	1
values[2]	529	1			T15	4		T18	21		T52	4
values[3]	808	1			T14	13		T20	3		T40	33
values[4]	568	1			T136	1		T122	20		T142	14
values[5]	731	1			T11	6		T58	1		T93	6
values[6]	564	1			T12	2		T93	14		T66	26
values[7]	848	1			T38	13		T222	9		T136	1
values[8]	3105	1			T16	1		T17	17		T19	28
values[9]	1070	1			T13	9		T20	3		T87	5
minimum	14576	1			T1	20		T2	3		T4	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	628	1			T15	4		T18	21		T87	8
values[1]	579	1			T52	4		T95	23		T44	4
values[2]	747	1			T14	13		T20	3		T40	33
values[3]	625	1			T58	1		T91	23		T120	1
values[4]	657	1			T11	6		T93	6		T95	23
values[5]	747	1			T12	2		T93	14		T66	26
values[6]	3039	1			T16	1		T17	17		T19	28
values[7]	781	1			T43	2		T135	1		T121	8
values[8]	646	1			T13	9		T20	3		T53	14
values[9]	296	1			T87	5		T127	2		T183	10
minimum	14576	1			T1	20		T2	3		T4	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19298

1

T1

20

T2

3

T4

13

auto[1]

4023

1

T11

1

T14

12

T15

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T18	11		T53	17		T132	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T15	3		T87	1		T121	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T52	4		T44	3		T150	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T95	11		T45	2		T128	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T42	3		T149	1		T127	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T14	13		T20	2		T40	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T58	1		T120	1		T128	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T91	10		T136	1		T129	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T11	6		T95	11		T122	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T93	1		T38	3		T119	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T66	14		T222	9		T120	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T12	1		T93	8		T177	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1710	1			T16	1		T17	2		T19	28
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T38	8		T163	2		T133	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T43	2		T231	9		T183	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T135	1		T121	1		T184	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T20	2		T66	2		T126	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T13	1		T53	14		T119	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T87	1		T275	1		T286	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T127	2		T183	7		T278	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14491	1			T1	20		T2	3		T4	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T18	10		T132	9		T228	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T15	1		T87	7		T121	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T44	1		T150	16		T131	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T95	12		T133	13		T169	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T177	3		T169	11		T251	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T20	1		T40	18		T117	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T142	13		T244	1		T232	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T91	13		T252	19		T157	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T95	12		T219	1		T185	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T93	5		T38	6		T215	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T66	12		T221	12		T130	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T12	1		T93	6		T177	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1031	1			T17	15		T41	8		T88	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T38	5		T133	11		T226	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T231	3		T183	12		T132	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T121	7		T239	6		T211	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T20	1		T66	4		T126	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T13	8		T215	1		T252	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T87	4		T286	15		T314	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T183	3		T278	11		T158	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T13	5		T15	3		T38	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T219	4		T272	1		T315	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T183	7		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T39	1		T272	1		T316	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T87	1		T131	1		T171	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T53	17		T28	1		T228	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T121	1		T237	1		T167	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T18	11		T52	4		T44	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T15	3		T45	2		T46	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T42	3		T149	1		T120	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T14	13		T20	2		T40	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T122	17		T142	1		T251	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T136	1		T122	3		T274	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T11	6		T58	1		T95	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T93	1		T119	1		T215	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T66	14		T120	1		T130	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T12	1		T93	8		T38	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T222	9		T136	1		T221	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T38	8		T133	1		T169	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1728	1			T16	1		T17	2		T19	28
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T53	14		T135	1		T163	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	361	1			T20	2		T87	1		T66	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T13	1		T119	1		T135	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14491	1			T1	20		T2	3		T4	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T219	9		T315	10		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T183	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T39	4		T316	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T87	7		T131	9		T171	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T228	11		T185	5		T256	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T121	9		T289	5		T276	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T18	10		T44	1		T150	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T15	1		T133	2		T239	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T227	10		T278	12		T253	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T20	1		T40	18		T117	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T142	13		T251	10		T244	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T252	19		T256	6		T229	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T95	12		T219	1		T185	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T93	5		T215	9		T130	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T66	12		T130	13		T142	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T12	1		T93	6		T38	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T221	12		T131	5		T138	22
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T38	5		T133	11		T169	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1108	1			T17	15		T41	8		T88	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T251	1		T239	6		T211	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T20	1		T87	4		T66	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T13	8		T121	7		T215	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T13	5		T15	3		T38	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T18	11		T53	1		T132	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T15	3		T87	8		T121	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T52	1		T44	4		T150	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T95	13		T45	2		T128	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T42	3		T149	1		T127	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T14	1		T20	3		T40	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T58	1		T120	1		T128	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T91	14		T136	1		T129	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T11	5		T95	13		T122	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T93	6		T38	7		T119	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T66	13		T222	1		T120	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T12	2		T93	7		T177	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1375	1			T16	1		T17	17		T19	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T38	6		T163	2		T133	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T43	2		T231	4		T183	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T135	1		T121	8		T184	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T20	2		T66	5		T126	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T13	9		T53	1		T119	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T87	5		T275	1		T286	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T127	1		T183	4		T278	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14576	1			T1	20		T2	3		T4	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T18	10		T53	16		T132	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T15	1		T167	7		T276	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T52	3		T150	16		T132	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T95	10		T169	15		T140	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T177	10		T167	7		T169	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T14	12		T40	14		T118	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T266	16		T218	13		T242	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T91	9		T252	19		T265	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T11	1		T95	10		T122	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T38	2		T215	10		T128	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T66	13		T222	8		T240	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T93	7		T177	9		T169	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1366	1			T19	25		T243	8		T154	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T38	7		T226	13		T214	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T231	8		T183	12		T132	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T239	10		T211	9		T224	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T20	1		T66	1		T216	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T53	13		T252	12		T146	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T286	13		T314	8		T254	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T127	1		T183	6		T158	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T219	10		T272	1		T315	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T183	4		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T39	5		T272	1		T316	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T87	8		T131	10		T171	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T53	1		T28	1		T228	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T121	10		T237	1		T167	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T18	11		T52	1		T44	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T15	3		T45	2		T46	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T42	3		T149	1		T120	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T14	1		T20	3		T40	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T122	1		T142	14		T251	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T136	1		T122	1		T274	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T11	5		T58	1		T95	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T93	6		T119	1		T215	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T66	13		T120	1		T130	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T12	2		T93	7		T38	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T222	1		T136	1		T221	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T38	6		T133	12		T169	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1453	1			T16	1		T17	17		T19	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T53	1		T135	1		T163	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T20	2		T87	5		T66	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	338	1			T13	9		T119	1		T135	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14576	1			T1	20		T2	3		T4	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T219	3		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T183	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T317	21		T318	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T53	16		T228	12		T185	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T167	7		T276	13		T282	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T18	10		T52	3		T150	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T15	1		T140	11		T258	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T167	7		T227	9		T246	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T14	12		T40	14		T91	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T122	16		T251	8		T266	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T122	2		T252	19		T229	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T11	1		T95	10		T185	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T215	10		T265	7		T285	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T66	13		T144	7		T70	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T93	7		T38	2		T128	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T222	8		T144	6		T138	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T38	7		T169	13		T226	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1383	1			T19	25		T243	8		T154	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T53	13		T239	10		T211	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T20	1		T66	1		T216	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T127	1		T252	12		T146	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19298

1

T1

20

T2

3

T4

13

auto[1]

auto[0]

4023

1

T11

1

T14

12

T15

1