Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23321

1

T1

20

T2

3

T4

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19884

1

T1

20

T2

3

T4

13

auto[ADC_CTRL_FILTER_COND_OUT]

3437

1

T13

9

T15

4

T18

21

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17103

1

T1

20

T2

3

T4

13

auto[1]

6218

1

T11

1

T12

3

T16

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19493

1

T1

20

T2

3

T4

13

auto[1]

3828

1

T12

1

T13

13

T15

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	294	1			T11	1		T12	3		T42	1
values[0]	106	1			T44	4		T132	27		T138	20
values[1]	755	1			T18	21		T58	1		T136	1
values[2]	2810	1			T16	1		T17	17		T19	28
values[3]	615	1			T95	23		T136	1		T122	3
values[4]	660	1			T20	3		T117	8		T53	17
values[5]	617	1			T91	23		T38	13		T150	33
values[6]	563	1			T11	6		T15	4		T52	4
values[7]	661	1			T14	13		T93	6		T119	1
values[8]	753	1			T13	9		T20	3		T87	13
values[9]	1204	1			T12	2		T95	23		T43	2
minimum	14283	1			T1	20		T2	3		T4	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	905	1			T18	21		T58	1		T44	4
values[1]	2947	1			T16	1		T17	17		T19	28
values[2]	554	1			T95	23		T118	13		T120	1
values[3]	843	1			T20	3		T117	8		T53	17
values[4]	439	1			T66	6		T38	13		T150	33
values[5]	524	1			T11	6		T14	13		T15	4
values[6]	748	1			T13	9		T87	8		T93	6
values[7]	732	1			T87	5		T119	1		T135	2
values[8]	920	1			T12	2		T20	3		T222	9
values[9]	120	1			T95	23		T43	2		T135	1
minimum	14589	1			T1	20		T2	3		T4	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19298

1

T1

20

T2

3

T4

13

auto[1]

4023

1

T11

1

T14

12

T15

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T44	3		T130	1		T132	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T18	11		T58	1		T215	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1626	1			T16	1		T17	2		T19	28
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T53	14		T216	4		T136	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T118	13		T120	1		T136	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T95	11		T219	4		T319	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T20	2		T53	17		T66	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T117	1		T91	10		T128	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T66	2		T150	17		T120	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T38	8		T127	1		T138	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T11	6		T14	13		T128	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T15	3		T52	4		T42	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T144	7		T89	5		T240	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T13	1		T87	1		T93	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T87	1		T135	1		T122	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T119	1		T135	1		T274	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T12	1		T20	2		T126	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T222	9		T121	1		T183	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T95	11		T43	2		T273	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T135	1		T223	1		T308	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14491	1			T1	20		T2	3		T4	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T264	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T44	1		T130	10		T132	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T18	10		T215	9		T177	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1028	1			T17	15		T40	18		T41	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T169	14		T244	1		T39	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T226	14		T280	11		T320	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T95	12		T219	9		T146	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T20	1		T66	12		T133	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T117	7		T91	13		T131	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T66	4		T150	16		T215	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T38	5		T138	12		T240	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T132	14		T232	1		T255	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T15	1		T177	9		T183	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T89	2		T240	9		T239	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T13	8		T87	7		T93	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T87	4		T231	3		T244	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T218	10		T255	7		T209	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T12	1		T20	1		T126	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T121	7		T183	3		T131	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T95	12		T321	15		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T223	13		T308	12		T322	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T13	5		T15	3		T38	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T264	5		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T11	1		T12	3		T42	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T323	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T44	3		T132	12		T138	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T324	1		T246	14		T313	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T130	1		T252	20		T269	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T18	11		T58	1		T136	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1637	1			T16	1		T17	2		T19	28
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T53	14		T216	4		T127	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T136	1		T122	3		T46	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T95	11		T219	4		T319	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T20	2		T53	17		T66	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T117	1		T128	1		T131	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T150	17		T120	1		T215	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T91	10		T38	8		T127	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T11	6		T66	2		T120	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T15	3		T52	4		T42	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T14	13		T144	7		T89	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T93	1		T119	1		T220	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T20	2		T87	1		T122	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T13	1		T87	1		T119	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T12	1		T95	11		T43	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T222	9		T135	1		T121	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14198	1			T1	20		T2	3		T4	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T44	1		T132	15		T138	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T325	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T130	10		T252	19		T307	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T18	10		T215	9		T177	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	990	1			T17	15		T40	18		T41	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T169	14		T244	1		T326	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T226	14		T238	2		T239	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T95	12		T219	9		T39	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T20	1		T66	12		T256	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T117	7		T131	9		T146	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T150	16		T215	1		T133	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T91	13		T38	5		T138	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T66	4		T132	14		T133	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T15	1		T177	9		T183	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T89	2		T239	1		T157	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T93	5		T228	1		T185	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T20	1		T87	4		T231	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T13	8		T87	7		T219	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T12	1		T95	12		T126	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	349	1			T121	7		T183	3		T131	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T13	5		T15	3		T38	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T44	4		T130	11		T132	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T18	11		T58	1		T215	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1377	1			T16	1		T17	17		T19	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T53	1		T216	1		T136	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T118	1		T120	1		T136	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T95	13		T219	10		T319	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T20	2		T53	1		T66	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T117	8		T91	14		T128	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T66	5		T150	17		T120	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T38	6		T127	1		T138	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T11	5		T14	1		T128	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T15	3		T52	1		T42	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T144	1		T89	6		T240	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T13	9		T87	8		T93	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T87	5		T135	1		T122	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T119	1		T135	1		T274	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T12	2		T20	3		T126	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T222	1		T121	8		T183	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T95	13		T43	2		T273	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T135	1		T223	14		T308	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14576	1			T1	20		T2	3		T4	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T264	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T132	11		T169	9		T144	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T18	10		T215	10		T177	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1277	1			T19	25		T40	14		T93	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T53	13		T216	3		T127	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T118	12		T122	2		T226	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T95	10		T219	3		T327	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T20	1		T53	16		T66	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T91	9		T167	7		T262	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T66	1		T150	16		T169	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T38	7		T138	15		T240	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T11	1		T14	12		T128	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T15	1		T52	3		T177	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T144	6		T89	1		T240	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T219	12		T228	13		T185	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T122	16		T231	8		T244	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T266	4		T218	13		T242	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T245	4		T251	8		T228	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T222	8		T183	6		T167	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T95	10		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T308	3		T322	3		T328	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T264	7		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T11	1		T12	3		T42	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T323	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T44	4		T132	16		T138	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T324	1		T246	1		T313	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T130	11		T252	20		T269	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T18	11		T58	1		T136	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1332	1			T16	1		T17	17		T19	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T53	1		T216	1		T127	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T136	1		T122	1		T46	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T95	13		T219	10		T319	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T20	2		T53	1		T66	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T117	8		T128	1		T131	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T150	17		T120	1		T215	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T91	14		T38	6		T127	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T11	5		T66	5		T120	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T15	3		T52	1		T42	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T14	1		T144	1		T89	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T93	6		T119	1		T220	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T20	3		T87	5		T122	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T13	9		T87	8		T119	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	343	1			T12	2		T95	13		T43	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	414	1			T222	1		T135	1		T121	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14283	1			T1	20		T2	3		T4	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T132	11		T138	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T246	13		T313	11		T329	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T252	19		T269	17		T214	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T18	10		T215	10		T177	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1295	1			T19	25		T40	14		T93	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T53	13		T216	3		T127	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T122	2		T226	13		T245	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T95	10		T219	3		T327	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T20	1		T53	16		T66	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T167	7		T330	14		T146	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T150	16		T252	2		T247	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T91	9		T38	7		T138	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T11	1		T66	1		T128	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T15	1		T52	3		T177	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T14	12		T144	6		T89	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T228	13		T185	18		T212	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T122	16		T231	8		T240	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T219	12		T266	4		T242	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T95	10		T245	4		T251	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T222	8		T183	6		T167	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19298

1

T1

20

T2

3

T4

13

auto[1]

auto[0]

4023

1

T11

1

T14

12

T15

1