Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23321

1

T1

20

T2

3

T4

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19911

1

T1

20

T2

3

T4

13

auto[ADC_CTRL_FILTER_COND_OUT]

3410

1

T11

6

T13

9

T15

4

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17690

1

T1

20

T2

3

T4

13

auto[1]

5631

1

T13

9

T16

1

T17

17

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19493

1

T1

20

T2

3

T4

13

auto[1]

3828

1

T12

1

T13

13

T15

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	205	1			T128	1		T177	19		T131	6
values[0]	36	1			T14	13		T308	23		-	-
values[1]	708	1			T20	3		T38	13		T215	20
values[2]	445	1			T53	14		T237	1		T48	3
values[3]	798	1			T87	8		T52	4		T95	23
values[4]	774	1			T20	3		T53	17		T93	6
values[5]	3023	1			T13	9		T16	1		T17	17
values[6]	562	1			T42	3		T93	14		T43	2
values[7]	712	1			T11	6		T58	1		T91	23
values[8]	636	1			T15	4		T87	5		T117	8
values[9]	846	1			T12	2		T18	21		T66	6
minimum	14576	1			T1	20		T2	3		T4	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	584	1			T20	3		T215	20		T122	3
values[1]	596	1			T53	14		T122	17		T237	1
values[2]	803	1			T20	3		T87	8		T52	4
values[3]	3041	1			T16	1		T17	17		T19	28
values[4]	654	1			T13	9		T93	14		T66	26
values[5]	558	1			T58	1		T42	3		T43	2
values[6]	757	1			T11	6		T15	4		T117	8
values[7]	584	1			T87	5		T38	9		T222	9
values[8]	855	1			T12	2		T18	21		T118	13
values[9]	89	1			T66	6		T245	5		T214	12
minimum	14800	1			T1	20		T2	3		T4	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19298

1

T1

20

T2

3

T4

13

auto[1]

4023

1

T11

1

T14

12

T15

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T20	2		T131	1		T256	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T215	11		T122	3		T133	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T53	14		T122	17		T183	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T237	1		T48	3		T132	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T87	1		T52	4		T95	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T20	2		T216	4		T128	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1651	1			T16	1		T17	2		T19	28
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T40	15		T93	1		T126	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T131	1		T163	2		T281	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T13	1		T93	8		T66	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T58	1		T42	3		T149	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T43	2		T45	2		T252	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T117	1		T135	1		T231	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T11	6		T15	3		T91	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T38	3		T222	9		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T87	1		T44	3		T136	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T12	1		T18	11		T118	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T119	1		T150	17		T120	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T214	12		T330	13		T233	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T66	2		T245	5		T331	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14571	1			T1	20		T2	3		T4	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T132	9		T228	14		T217	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T20	1		T131	3		T256	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T215	9		T133	11		T252	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T183	3		T219	1		T138	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T132	14		T262	10		T241	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T87	7		T95	12		T130	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T20	1		T132	15		T133	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1022	1			T17	15		T41	8		T88	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T40	18		T93	5		T126	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T131	9		T227	10		T185	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T13	8		T93	6		T66	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T139	12		T229	2		T230	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T252	11		T170	5		T286	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T117	7		T231	3		T177	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T15	1		T91	13		T142	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T38	6		T221	12		T169	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T87	4		T44	1		T226	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T12	1		T18	10		T121	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T150	16		T177	9		T183	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T233	14		T291	10		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T66	4		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T13	5		T15	3		T38	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T132	9		T228	1		T295	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T128	1		T39	6		T31	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T177	10		T131	1		T169	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T14	13		T308	11		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T20	2		T38	8		T122	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T215	11		T122	3		T132	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T53	14		T131	1		T219	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T237	1		T48	3		T132	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T87	1		T52	4		T95	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T216	4		T128	1		T132	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T53	17		T95	11		T215	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T20	2		T93	1		T220	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1593	1			T16	1		T17	2		T19	28
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T13	1		T40	15		T66	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T42	3		T149	1		T136	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T93	8		T43	2		T252	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T58	1		T135	1		T231	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T11	6		T91	10		T120	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T117	1		T38	3		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T15	3		T87	1		T44	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T12	1		T18	11		T222	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T66	2		T119	1		T150	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14491	1			T1	20		T2	3		T4	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T39	5		T332	2		T321	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T177	9		T131	5		T169	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T308	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T20	1		T38	5		T239	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T215	9		T132	9		T133	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T131	3		T219	1		T138	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T132	14		T262	10		T257	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T87	7		T95	12		T130	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T132	15		T133	2		T169	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T95	12		T215	1		T251	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T20	1		T93	5		T133	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	971	1			T17	15		T41	8		T88	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T13	8		T40	18		T66	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T139	12		T229	2		T171	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T93	6		T252	11		T286	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T231	3		T177	3		T240	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T91	13		T219	9		T276	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T117	7		T38	6		T221	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T15	1		T87	4		T44	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T12	1		T18	10		T121	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T66	4		T150	16		T183	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T13	5		T15	3		T38	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T20	3		T131	4		T256	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T215	10		T122	1		T133	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T53	1		T122	1		T183	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T237	1		T48	3		T132	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T87	8		T52	1		T95	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T20	2		T216	1		T128	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1359	1			T16	1		T17	17		T19	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T40	19		T93	6		T126	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T131	10		T163	2		T281	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T13	9		T93	7		T66	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T58	1		T42	3		T149	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T43	2		T45	2		T252	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T117	8		T135	1		T231	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T11	5		T15	3		T91	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T38	7		T222	1		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T87	5		T44	4		T136	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T12	2		T18	11		T118	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T119	1		T150	17		T120	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T214	1		T330	1		T233	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T66	5		T245	1		T331	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14633	1			T1	20		T2	3		T4	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T132	10		T228	2		T217	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T140	11		T146	10		T305	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T215	10		T122	2		T252	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T53	13		T122	16		T183	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T132	14		T262	8		T282	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T52	3		T95	10		T144	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T20	1		T216	3		T132	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1314	1			T19	25		T53	16		T95	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T40	14		T138	15		T240	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T227	9		T185	6		T269	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T93	7		T66	13		T239	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T167	7		T266	12		T327	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T252	12		T170	5		T286	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T231	8		T177	10		T240	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T11	1		T15	1		T91	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T38	2		T222	8		T128	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T226	13		T70	1		T170	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T18	10		T118	12		T39	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T150	16		T127	1		T177	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T214	11		T330	12		T233	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T66	1		T245	4		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T14	12		T38	7		T280	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T132	8		T228	13		T295	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T128	1		T39	6		T31	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T177	10		T131	6		T169	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T14	1		T308	13		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T20	3		T38	6		T122	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T215	10		T122	1		T132	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T53	1		T131	4		T219	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T237	1		T48	3		T132	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T87	8		T52	1		T95	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T216	1		T128	1		T132	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T53	1		T95	13		T215	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T20	2		T93	6		T220	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1301	1			T16	1		T17	17		T19	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T13	9		T40	19		T66	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T42	3		T149	1		T136	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T93	7		T43	2		T252	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T58	1		T135	1		T231	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T11	5		T91	14		T120	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T117	8		T38	7		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T15	3		T87	5		T44	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T12	2		T18	11		T222	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T66	5		T119	1		T150	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14576	1			T1	20		T2	3		T4	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T39	5		T332	2		T291	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T177	9		T169	9		T219	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T14	12		T308	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T38	7		T122	16		T140	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T215	10		T122	2		T132	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T53	13		T138	9		T239	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T132	14		T262	8		T313	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T52	3		T95	10		T183	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T216	3		T132	11		T169	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T53	16		T95	10		T167	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T20	1		T138	21		T245	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1263	1			T19	25		T243	8		T154	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T40	14		T66	13		T240	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T266	12		T327	2		T246	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T93	7		T252	12		T286	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T231	8		T177	10		T167	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T11	1		T91	9		T219	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T38	2		T128	7		T169	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T15	1		T226	13		T70	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T18	10		T222	8		T118	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T66	1		T150	16		T127	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19298

1

T1

20

T2

3

T4

13

auto[1]

auto[0]

4023

1

T11

1

T14

12

T15

1