Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	5529	1			T1	20		T3	20		T4	8
testmodes[AdcCtrlTestmodeNormal]	4855	1			T4	3		T5	5		T6	1
testmodes[AdcCtrlTestmodeLowpower]	4950	1			T6	1		T8	15		T10	5
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	2739	1			T1	19		T3	19		T4	6
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1493	1			T4	2		T5	3		T6	1
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1193	1			T10	1		T13	1		T38	3
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1459	1			T4	1		T5	2		T9	3
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	1766	1			T4	1		T5	2		T9	1
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1287	1			T6	1		T10	1		T38	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1218	1			T10	1		T38	3		T43	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1254	1			T10	1		T11	1		T38	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2230	1			T8	14		T10	2		T11	2