Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.70 99.07 96.67 100.00 100.00 98.82 98.33 90.99


Total tests in report: 917
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
73.39 73.39 96.93 96.93 81.27 81.27 87.56 87.56 48.65 48.65 95.72 95.72 89.32 89.32 14.32 14.32 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.2902794237
80.64 7.24 98.39 1.46 85.47 4.20 96.33 8.77 75.68 27.03 97.77 2.05 90.98 1.67 19.84 5.52 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.797586552
83.93 3.30 98.85 0.46 93.58 8.11 96.80 0.47 75.68 0.00 98.45 0.68 95.33 4.34 28.85 9.01 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_clock_gating.3784484088
86.80 2.86 98.85 0.00 93.62 0.04 96.80 0.00 94.59 18.92 98.51 0.06 95.33 0.00 29.87 1.02 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_fsm_reset.3256083119
88.05 1.25 98.85 0.00 93.70 0.08 96.80 0.00 94.59 0.00 98.51 0.00 95.33 0.00 38.53 8.66 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_stress_all.1793188336
89.03 0.99 98.85 0.00 93.74 0.04 97.04 0.24 97.30 2.70 98.51 0.00 95.49 0.17 42.30 3.77 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.2886256050
89.94 0.90 98.85 0.00 93.78 0.04 97.04 0.00 97.30 0.00 98.51 0.00 95.66 0.17 48.42 6.11 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_both.519098030
90.61 0.67 98.85 0.00 93.87 0.08 97.04 0.00 97.30 0.00 98.51 0.00 95.66 0.00 53.06 4.64 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_stress_all.2086628276
91.19 0.58 98.85 0.00 93.87 0.00 97.04 0.00 97.30 0.00 98.51 0.00 95.66 0.00 57.13 4.07 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_stress_all.827163083
91.72 0.53 98.85 0.00 94.03 0.16 97.04 0.00 97.30 0.00 98.51 0.00 95.66 0.00 60.64 3.52 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_both.3581418942
92.17 0.45 98.85 0.00 94.03 0.00 97.04 0.00 100.00 2.70 98.51 0.00 95.66 0.00 61.12 0.47 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.3624903804
92.62 0.45 98.88 0.03 94.15 0.12 99.17 2.13 100.00 0.00 98.57 0.06 96.33 0.67 61.24 0.12 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_sec_cm.1601274574
93.07 0.45 98.88 0.00 94.15 0.00 99.17 0.00 100.00 0.00 98.57 0.00 96.33 0.00 64.36 3.12 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_both.972090919
93.50 0.44 98.88 0.00 95.35 1.19 99.64 0.47 100.00 0.00 98.63 0.06 96.99 0.67 65.01 0.65 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_errors.3064658302
93.88 0.38 98.88 0.00 95.35 0.00 99.64 0.00 100.00 0.00 98.63 0.00 96.99 0.00 67.66 2.65 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_clock_gating.4215912683
94.19 0.31 98.88 0.00 95.35 0.00 99.64 0.00 100.00 0.00 98.63 0.00 96.99 0.00 69.80 2.15 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_interrupt.4037820409
94.48 0.29 98.88 0.00 95.47 0.12 99.64 0.00 100.00 0.00 98.63 0.00 96.99 0.00 71.70 1.90 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_interrupt_fixed.1964172375
94.76 0.28 98.88 0.00 95.47 0.00 99.64 0.00 100.00 0.00 98.63 0.00 96.99 0.00 73.67 1.97 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_stress_all.883188567
94.99 0.23 98.88 0.00 95.47 0.00 99.64 0.00 100.00 0.00 98.63 0.00 96.99 0.00 75.29 1.62 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_clock_gating.867994488
95.21 0.22 98.95 0.06 95.64 0.16 99.64 0.00 100.00 0.00 98.76 0.12 98.16 1.17 75.29 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_rw.3507320779
95.39 0.18 98.95 0.00 95.64 0.00 99.64 0.00 100.00 0.00 98.76 0.00 98.16 0.00 76.57 1.27 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_stress_all.2782539721
95.55 0.16 98.95 0.00 95.64 0.00 99.64 0.00 100.00 0.00 98.76 0.00 98.16 0.00 77.69 1.12 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_both.3797245322
95.70 0.15 98.95 0.00 95.64 0.00 99.64 0.00 100.00 0.00 98.76 0.00 98.16 0.00 78.76 1.07 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_clock_gating.4292293804
95.83 0.13 98.98 0.03 95.92 0.29 99.76 0.12 100.00 0.00 98.82 0.06 98.16 0.00 79.19 0.42 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.574529716
95.97 0.13 98.98 0.00 95.92 0.00 99.76 0.00 100.00 0.00 98.82 0.00 98.16 0.00 80.11 0.92 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_wakeup.3584976063
96.08 0.12 98.98 0.00 95.92 0.00 99.76 0.00 100.00 0.00 98.82 0.00 98.16 0.00 80.93 0.82 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_clock_gating.3058174538
96.19 0.11 98.98 0.00 95.92 0.00 99.76 0.00 100.00 0.00 98.82 0.00 98.16 0.00 81.68 0.75 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_wakeup.1845032249
96.28 0.09 98.98 0.00 95.92 0.00 99.76 0.00 100.00 0.00 98.82 0.00 98.16 0.00 82.28 0.60 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_clock_gating.2170066134
96.36 0.08 98.98 0.00 95.92 0.00 99.76 0.00 100.00 0.00 98.82 0.00 98.16 0.00 82.86 0.57 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_both.649403971
96.43 0.07 98.98 0.00 95.92 0.00 99.76 0.00 100.00 0.00 98.82 0.00 98.16 0.00 83.38 0.52 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_wakeup_fixed.1941339616
96.50 0.07 98.98 0.00 95.92 0.00 99.76 0.00 100.00 0.00 98.82 0.00 98.16 0.00 83.88 0.50 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_both.3588193448
96.57 0.07 98.98 0.00 95.92 0.00 99.76 0.00 100.00 0.00 98.82 0.00 98.16 0.00 84.35 0.47 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.413000921
96.64 0.06 99.07 0.09 96.05 0.12 100.00 0.24 100.00 0.00 98.82 0.00 98.16 0.00 84.35 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_alert_test.274752497
96.70 0.06 99.07 0.00 96.34 0.29 100.00 0.00 100.00 0.00 98.82 0.00 98.16 0.00 84.50 0.15 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.2071495096
96.76 0.06 99.07 0.00 96.34 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.16 0.00 84.90 0.40 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_interrupt.3686980597
96.80 0.05 99.07 0.00 96.34 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.16 0.00 85.23 0.32 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_both.2577174868
96.85 0.04 99.07 0.00 96.34 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.16 0.00 85.53 0.30 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_clock_gating.1801671438
96.88 0.04 99.07 0.00 96.34 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.16 0.00 85.80 0.27 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_fsm_reset.2861691413
96.92 0.04 99.07 0.00 96.34 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.16 0.00 86.07 0.27 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_both.2999003221
96.96 0.04 99.07 0.00 96.34 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.16 0.00 86.32 0.25 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_interrupt.1200529213
96.99 0.04 99.07 0.00 96.42 0.08 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.17 86.32 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.128207030
97.03 0.04 99.07 0.00 96.67 0.25 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 86.32 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_tl_errors.3309334359
97.06 0.03 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 86.55 0.22 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_wakeup.1531847929
97.09 0.03 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 86.77 0.22 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_both.16675357
97.13 0.03 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 87.00 0.22 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_both.3566454788
97.15 0.03 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 87.20 0.20 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_polled.1650454450
97.18 0.03 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 87.40 0.20 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_wakeup.1103530067
97.21 0.03 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 87.60 0.20 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_stress_all.3252577496
97.24 0.03 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 87.80 0.20 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.3493828632
97.27 0.02 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 87.97 0.17 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_interrupt.3450116123
97.29 0.02 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 88.15 0.17 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_interrupt.914720036
97.32 0.02 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 88.32 0.17 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_wakeup.4110600090
97.34 0.02 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 88.50 0.17 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_both.4012633485
97.36 0.02 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 88.64 0.15 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_clock_gating.3883270240
97.38 0.02 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 88.77 0.12 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.2979888075
97.39 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 88.87 0.10 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_stress_all.487721130
97.41 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 88.97 0.10 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_stress_all.642366107
97.42 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 89.07 0.10 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_clock_gating.152385443
97.44 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 89.17 0.10 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_both.152101942
97.45 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 89.27 0.10 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_wakeup.3015359021
97.47 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 89.37 0.10 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_interrupt.1199879733
97.48 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 89.47 0.10 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_interrupt.1366292755
97.49 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 89.54 0.07 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.385900239
97.50 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 89.62 0.07 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_polled.2306907989
97.51 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 89.69 0.07 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_stress_all.322763787
97.52 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 89.77 0.07 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_both.3160291791
97.53 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 89.84 0.07 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_interrupt.1200395236
97.54 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 89.92 0.07 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_interrupt.878534640
97.55 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 89.99 0.07 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_wakeup.1345145531
97.56 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.07 0.07 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_interrupt.2928616463
97.57 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.12 0.05 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_both.976748219
97.58 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.17 0.05 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_polled.1224294549
97.59 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.22 0.05 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_stress_all.1533478309
97.59 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.27 0.05 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.3705796427
97.60 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.32 0.05 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_fsm_reset.1017935256
97.61 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.37 0.05 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_polled.1916429341
97.61 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.42 0.05 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_wakeup.1886783908
97.62 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.47 0.05 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_wakeup.154414524
97.63 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.52 0.05 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_polled.3631849130
97.64 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.57 0.05 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_fsm_reset.261783981
97.64 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.62 0.05 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_fsm_reset.633564558
97.65 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.67 0.05 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_clock_gating.511513768
97.65 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.69 0.02 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_fsm_reset.2085324205
97.66 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.72 0.02 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.2374631421
97.66 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.74 0.02 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_wakeup.2750818573
97.66 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.77 0.02 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_clock_gating.2875310444
97.67 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.79 0.02 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_fsm_reset.3170809368
97.67 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.82 0.02 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_wakeup.4007682123
97.68 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.84 0.02 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_stress_all.1708748118
97.68 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.87 0.02 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_interrupt.1135432490
97.68 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.89 0.02 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_clock_gating.333539736
97.69 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.92 0.02 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.1907077146
97.69 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.94 0.02 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_clock_gating.2748293417
97.69 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.97 0.02 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_fsm_reset.3804661584
97.70 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.99 0.02 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.1657209905

Tests that do not contribute to grading

Name   
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.1325482735
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.2470732832
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2372273704
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.964986581
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_intr_test.382023511
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.529103825
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_errors.2926505144
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3299917665
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3504491954
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.1022587825
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.1805632618
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_rw.2270341954
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_intr_test.3598377990
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.2468351266
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.20938024
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.1359596895
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_rw.478917326
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_intr_test.3121901533
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.2843362046
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_errors.4177878052
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.515427769
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.1188141646
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_rw.1036567403
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_intr_test.2870263481
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.680989401
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_errors.125006931
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.521905591
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_rw.291220809
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_intr_test.369388674
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.2528513201
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_errors.2220988380
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.742895611
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.2572297427
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_rw.2169065031
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_intr_test.1504533245
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.3922925240
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_errors.2696235062
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3536659088
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.4081388709
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1265227915
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_intr_test.1802125102
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2763616218
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_errors.1460823548
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.561681611
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.2980297732
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_rw.1401948139
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_intr_test.2946781822
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.532793903
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1699759305
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.751666329
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.4011431033
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_rw.1672970727
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_intr_test.2058671578
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.1450882556
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_errors.813181117
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.764040759
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.1404069927
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_rw.3458106256
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_intr_test.172753761
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.2462053208
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_errors.3466077962
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3840754188
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.1374492457
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_csr_rw.643459693
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_intr_test.1899974864
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.3919871660
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1140861586
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.3980585994
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.1118614590
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_csr_rw.1119230309
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_intr_test.747998616
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.1931242724
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_tl_errors.94368987
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.1513084407
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.637845867
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.3631841995
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.2867386346
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.4163224210
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1703555608
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_intr_test.3874035771
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.1981001322
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_tl_errors.2208810563
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.592336614
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/20.adc_ctrl_intr_test.2796636180
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/21.adc_ctrl_intr_test.3543807138
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/22.adc_ctrl_intr_test.2311328846
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/23.adc_ctrl_intr_test.2305681621
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/24.adc_ctrl_intr_test.953617781
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/25.adc_ctrl_intr_test.2496306125
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/26.adc_ctrl_intr_test.2702721709
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/27.adc_ctrl_intr_test.1479464155
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/28.adc_ctrl_intr_test.311554048
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/29.adc_ctrl_intr_test.2864619238
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.2905381163
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.1491127770
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.542333127
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.972413789
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_rw.1521376396
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_intr_test.3500336668
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.573573598
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_tl_errors.2489728958
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.970903052
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/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_lowpower_counter.1716956142
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/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_poweron_counter.3742056455
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Total test records in report: 917
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_smoke.1047836857 Oct 12 01:13:45 AM UTC 24 Oct 12 01:13:56 AM UTC 24 5747716638 ps
T2 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_alert_test.3819577001 Oct 12 01:13:53 AM UTC 24 Oct 12 01:13:56 AM UTC 24 437913928 ps
T3 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_smoke.1854540048 Oct 12 01:13:53 AM UTC 24 Oct 12 01:13:58 AM UTC 24 5751407881 ps
T4 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_poweron_counter.3077107148 Oct 12 01:13:57 AM UTC 24 Oct 12 01:14:01 AM UTC 24 3357866111 ps
T19 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_sec_cm.1601274574 Oct 12 01:13:51 AM UTC 24 Oct 12 01:14:01 AM UTC 24 3742360925 ps
T20 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_alert_test.274752497 Oct 12 01:14:02 AM UTC 24 Oct 12 01:14:05 AM UTC 24 494921924 ps
T5 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_poweron_counter.793380648 Oct 12 01:13:51 AM UTC 24 Oct 12 01:14:09 AM UTC 24 3594313977 ps
T6 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.2902794237 Oct 12 01:14:00 AM UTC 24 Oct 12 01:14:10 AM UTC 24 5075424445 ps
T7 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_smoke.546876756 Oct 12 01:14:03 AM UTC 24 Oct 12 01:14:15 AM UTC 24 5790999446 ps
T8 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_lowpower_counter.1632985573 Oct 12 01:13:51 AM UTC 24 Oct 12 01:14:16 AM UTC 24 31735463299 ps
T9 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_poweron_counter.2586001459 Oct 12 01:14:14 AM UTC 24 Oct 12 01:14:18 AM UTC 24 3636206955 ps
T21 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_alert_test.1522772736 Oct 12 01:14:19 AM UTC 24 Oct 12 01:14:22 AM UTC 24 341807009 ps
T22 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_sec_cm.3756144601 Oct 12 01:14:02 AM UTC 24 Oct 12 01:14:25 AM UTC 24 8236421929 ps
T10 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.574529716 Oct 12 01:13:51 AM UTC 24 Oct 12 01:14:28 AM UTC 24 202062008496 ps
T11 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.797586552 Oct 12 01:14:17 AM UTC 24 Oct 12 01:14:36 AM UTC 24 31595602871 ps
T23 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_sec_cm.1380211785 Oct 12 01:14:18 AM UTC 24 Oct 12 01:14:37 AM UTC 24 4264345213 ps
T24 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_smoke.2984801301 Oct 12 01:14:23 AM UTC 24 Oct 12 01:14:40 AM UTC 24 5747623097 ps
T40 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_lowpower_counter.3275743828 Oct 12 01:14:16 AM UTC 24 Oct 12 01:14:42 AM UTC 24 30658816148 ps
T41 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_poweron_counter.2713001562 Oct 12 01:14:38 AM UTC 24 Oct 12 01:14:45 AM UTC 24 4712022051 ps
T42 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_alert_test.2889898042 Oct 12 01:14:42 AM UTC 24 Oct 12 01:14:46 AM UTC 24 354937799 ps
T12 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_both.2202627530 Oct 12 01:13:57 AM UTC 24 Oct 12 01:14:53 AM UTC 24 190489938834 ps
T13 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.2826270047 Oct 12 01:14:40 AM UTC 24 Oct 12 01:14:54 AM UTC 24 97031353944 ps
T14 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_clock_gating.3784484088 Oct 12 01:13:50 AM UTC 24 Oct 12 01:14:54 AM UTC 24 491248104015 ps
T82 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_smoke.4249706531 Oct 12 01:14:42 AM UTC 24 Oct 12 01:14:58 AM UTC 24 5984665325 ps
T83 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_poweron_counter.2930507995 Oct 12 01:14:57 AM UTC 24 Oct 12 01:15:03 AM UTC 24 3782728520 ps
T50 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_lowpower_counter.942368071 Oct 12 01:14:58 AM UTC 24 Oct 12 01:15:12 AM UTC 24 37252412135 ps
T77 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_alert_test.794680929 Oct 12 01:15:13 AM UTC 24 Oct 12 01:15:15 AM UTC 24 413956281 ps
T36 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.7065158 Oct 12 01:15:04 AM UTC 24 Oct 12 01:15:15 AM UTC 24 2347829236 ps
T78 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_sec_cm.3205983889 Oct 12 01:14:42 AM UTC 24 Oct 12 01:15:18 AM UTC 24 7348606136 ps
T15 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_polled_fixed.2703658489 Oct 12 01:14:25 AM UTC 24 Oct 12 01:15:18 AM UTC 24 324974143836 ps
T145 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_lowpower_counter.2735061687 Oct 12 01:14:38 AM UTC 24 Oct 12 01:15:22 AM UTC 24 41964464315 ps
T16 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_polled.1224294549 Oct 12 01:13:45 AM UTC 24 Oct 12 01:15:23 AM UTC 24 324376048818 ps
T17 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_wakeup.2568711296 Oct 12 01:13:50 AM UTC 24 Oct 12 01:15:26 AM UTC 24 184311416861 ps
T368 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_smoke.814054302 Oct 12 01:15:13 AM UTC 24 Oct 12 01:15:27 AM UTC 24 5848689949 ps
T79 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_sec_cm.320665433 Oct 12 01:15:07 AM UTC 24 Oct 12 01:15:29 AM UTC 24 8121188760 ps
T369 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_poweron_counter.47748453 Oct 12 01:15:30 AM UTC 24 Oct 12 01:15:37 AM UTC 24 4738943894 ps
T370 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_lowpower_counter.1531601611 Oct 12 01:13:58 AM UTC 24 Oct 12 01:15:49 AM UTC 24 43239068160 ps
T18 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_interrupt_fixed.1964172375 Oct 12 01:13:49 AM UTC 24 Oct 12 01:15:56 AM UTC 24 320331252300 ps
T371 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_alert_test.405010165 Oct 12 01:15:56 AM UTC 24 Oct 12 01:15:58 AM UTC 24 358481894 ps
T37 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_interrupt.1625851934 Oct 12 01:13:53 AM UTC 24 Oct 12 01:16:05 AM UTC 24 163540126564 ps
T372 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_smoke.537526762 Oct 12 01:15:59 AM UTC 24 Oct 12 01:16:08 AM UTC 24 5999780127 ps
T38 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.2886256050 Oct 12 01:15:37 AM UTC 24 Oct 12 01:16:38 AM UTC 24 38407086973 ps
T34 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_stress_all.2452975280 Oct 12 01:15:06 AM UTC 24 Oct 12 01:16:42 AM UTC 24 485578821111 ps
T373 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_lowpower_counter.3913535957 Oct 12 01:15:34 AM UTC 24 Oct 12 01:16:48 AM UTC 24 36330465676 ps
T80 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_polled.1379608244 Oct 12 01:13:53 AM UTC 24 Oct 12 01:17:11 AM UTC 24 332749400119 ps
T81 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_interrupt.455423886 Oct 12 01:14:07 AM UTC 24 Oct 12 01:17:14 AM UTC 24 165258523098 ps
T172 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_poweron_counter.3321362239 Oct 12 01:17:15 AM UTC 24 Oct 12 01:17:18 AM UTC 24 4934020347 ps
T132 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_polled.3427052751 Oct 12 01:14:45 AM UTC 24 Oct 12 01:17:26 AM UTC 24 166453367900 ps
T166 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_polled_fixed.95637061 Oct 12 01:13:47 AM UTC 24 Oct 12 01:17:36 AM UTC 24 327667153144 ps
T173 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_lowpower_counter.571677723 Oct 12 01:17:19 AM UTC 24 Oct 12 01:17:44 AM UTC 24 31157378871 ps
T45 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_both.3581418942 Oct 12 01:14:34 AM UTC 24 Oct 12 01:17:46 AM UTC 24 493417045714 ps
T174 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_alert_test.3087239011 Oct 12 01:17:47 AM UTC 24 Oct 12 01:17:50 AM UTC 24 518978933 ps
T175 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_interrupt_fixed.166550460 Oct 12 01:14:52 AM UTC 24 Oct 12 01:17:50 AM UTC 24 163602740365 ps
T46 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_both.976748219 Oct 12 01:13:50 AM UTC 24 Oct 12 01:17:51 AM UTC 24 182718235615 ps
T130 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_wakeup.1618361649 Oct 12 01:15:23 AM UTC 24 Oct 12 01:17:52 AM UTC 24 395948360742 ps
T186 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_polled.1683183566 Oct 12 01:14:03 AM UTC 24 Oct 12 01:17:59 AM UTC 24 166853922630 ps
T374 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_smoke.2804920397 Oct 12 01:17:50 AM UTC 24 Oct 12 01:17:59 AM UTC 24 5638186120 ps
T39 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.3973115615 Oct 12 01:17:37 AM UTC 24 Oct 12 01:18:05 AM UTC 24 2861356732 ps
T138 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_interrupt.1135432490 Oct 12 01:14:26 AM UTC 24 Oct 12 01:18:08 AM UTC 24 499654225780 ps
T375 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_polled_fixed.3577859847 Oct 12 01:14:46 AM UTC 24 Oct 12 01:18:09 AM UTC 24 161269773907 ps
T376 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_poweron_counter.827851086 Oct 12 01:18:10 AM UTC 24 Oct 12 01:18:16 AM UTC 24 4503916182 ps
T139 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_polled.2388386453 Oct 12 01:15:16 AM UTC 24 Oct 12 01:18:21 AM UTC 24 326774589399 ps
T131 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_stress_all.2086628276 Oct 12 01:15:51 AM UTC 24 Oct 12 01:18:27 AM UTC 24 357267358253 ps
T154 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_wakeup_fixed.1941339616 Oct 12 01:13:50 AM UTC 24 Oct 12 01:18:27 AM UTC 24 394831405529 ps
T216 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_wakeup_fixed.3476543805 Oct 12 01:16:44 AM UTC 24 Oct 12 01:18:49 AM UTC 24 195742039509 ps
T377 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_alert_test.1950931650 Oct 12 01:18:49 AM UTC 24 Oct 12 01:18:52 AM UTC 24 527044173 ps
T133 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_stress_all.1793188336 Oct 12 01:13:51 AM UTC 24 Oct 12 01:18:55 AM UTC 24 501409154327 ps
T43 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.4109610440 Oct 12 01:18:27 AM UTC 24 Oct 12 01:18:55 AM UTC 24 32737858715 ps
T378 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_lowpower_counter.1716956142 Oct 12 01:18:17 AM UTC 24 Oct 12 01:18:56 AM UTC 24 36487603270 ps
T379 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_smoke.1550811286 Oct 12 01:18:52 AM UTC 24 Oct 12 01:19:00 AM UTC 24 5750361320 ps
T146 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_wakeup_fixed.169476370 Oct 12 01:15:25 AM UTC 24 Oct 12 01:19:08 AM UTC 24 200560455307 ps
T198 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_clock_gating.1406088001 Oct 12 01:16:49 AM UTC 24 Oct 12 01:19:17 AM UTC 24 180912592264 ps
T147 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_wakeup.4110600090 Oct 12 01:14:54 AM UTC 24 Oct 12 01:19:38 AM UTC 24 369158743120 ps
T191 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_interrupt.2928616463 Oct 12 01:16:09 AM UTC 24 Oct 12 01:20:23 AM UTC 24 327350433606 ps
T380 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_poweron_counter.4078867978 Oct 12 01:20:24 AM UTC 24 Oct 12 01:20:28 AM UTC 24 2809226810 ps
T140 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_wakeup.3584976063 Oct 12 01:13:56 AM UTC 24 Oct 12 01:20:29 AM UTC 24 553316306555 ps
T176 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_interrupt.301918559 Oct 12 01:13:48 AM UTC 24 Oct 12 01:20:54 AM UTC 24 490198295416 ps
T253 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_interrupt_fixed.501992862 Oct 12 01:14:26 AM UTC 24 Oct 12 01:21:02 AM UTC 24 163369258572 ps
T44 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.605844828 Oct 12 01:20:55 AM UTC 24 Oct 12 01:21:05 AM UTC 24 1694544904 ps
T381 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_alert_test.4281960804 Oct 12 01:21:05 AM UTC 24 Oct 12 01:21:08 AM UTC 24 502804152 ps
T382 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_smoke.2176041084 Oct 12 01:21:09 AM UTC 24 Oct 12 01:21:14 AM UTC 24 5939956343 ps
T258 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_interrupt.1891574962 Oct 12 01:14:47 AM UTC 24 Oct 12 01:21:22 AM UTC 24 167402130347 ps
T134 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_clock_gating.2812896835 Oct 12 01:15:27 AM UTC 24 Oct 12 01:21:33 AM UTC 24 393210779013 ps
T383 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_interrupt_fixed.66297871 Oct 12 01:15:20 AM UTC 24 Oct 12 01:21:33 AM UTC 24 494738280064 ps
T384 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_lowpower_counter.693559083 Oct 12 01:20:29 AM UTC 24 Oct 12 01:21:36 AM UTC 24 28532708974 ps
T47 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_fsm_reset.3256083119 Oct 12 01:14:16 AM UTC 24 Oct 12 01:22:27 AM UTC 24 105810155891 ps
T135 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_polled.2203081930 Oct 12 01:14:23 AM UTC 24 Oct 12 01:22:31 AM UTC 24 167470051292 ps
T385 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_wakeup_fixed.948737109 Oct 12 01:14:10 AM UTC 24 Oct 12 01:22:32 AM UTC 24 199658670457 ps
T188 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_wakeup.1061764079 Oct 12 01:21:37 AM UTC 24 Oct 12 01:22:38 AM UTC 24 176512401046 ps
T386 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_polled_fixed.1202464651 Oct 12 01:16:06 AM UTC 24 Oct 12 01:22:45 AM UTC 24 165265677008 ps
T48 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_fsm_reset.730738237 Oct 12 01:15:03 AM UTC 24 Oct 12 01:22:47 AM UTC 24 75600880999 ps
T387 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_poweron_counter.3742056455 Oct 12 01:22:33 AM UTC 24 Oct 12 01:22:49 AM UTC 24 3377759810 ps
T388 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_wakeup_fixed.1718557747 Oct 12 01:14:29 AM UTC 24 Oct 12 01:22:52 AM UTC 24 414165993930 ps
T389 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_alert_test.1981999912 Oct 12 01:22:53 AM UTC 24 Oct 12 01:22:55 AM UTC 24 314064147 ps
T190 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_wakeup.1204931655 Oct 12 01:19:09 AM UTC 24 Oct 12 01:23:00 AM UTC 24 361701355352 ps
T390 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_lowpower_counter.1098009390 Oct 12 01:22:38 AM UTC 24 Oct 12 01:23:00 AM UTC 24 42845706605 ps
T148 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_both.649403971 Oct 12 01:17:12 AM UTC 24 Oct 12 01:23:03 AM UTC 24 359696334611 ps
T391 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_smoke.4276759445 Oct 12 01:22:56 AM UTC 24 Oct 12 01:23:11 AM UTC 24 5566539617 ps
T25 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.4252586873 Oct 12 01:22:47 AM UTC 24 Oct 12 01:23:26 AM UTC 24 15266320093 ps
T49 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_fsm_reset.633564558 Oct 12 01:15:36 AM UTC 24 Oct 12 01:23:33 AM UTC 24 71553073021 ps
T392 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_wakeup_fixed.999229754 Oct 12 01:22:03 AM UTC 24 Oct 12 01:23:35 AM UTC 24 208087893930 ps
T393 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_wakeup_fixed.3046687286 Oct 12 01:14:55 AM UTC 24 Oct 12 01:23:40 AM UTC 24 194106195224 ps
T215 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_clock_gating.511513768 Oct 12 01:19:38 AM UTC 24 Oct 12 01:23:44 AM UTC 24 331708708044 ps
T394 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_poweron_counter.3244844512 Oct 12 01:23:44 AM UTC 24 Oct 12 01:23:50 AM UTC 24 4414014351 ps
T189 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_clock_gating.239285609 Oct 12 01:14:55 AM UTC 24 Oct 12 01:24:11 AM UTC 24 339053105415 ps
T141 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_clock_gating.3317324467 Oct 12 01:18:06 AM UTC 24 Oct 12 01:24:11 AM UTC 24 158993049583 ps
T35 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_stress_all.487721130 Oct 12 01:14:17 AM UTC 24 Oct 12 01:24:20 AM UTC 24 138856272809 ps
T51 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_stress_all.172616466 Oct 12 01:14:41 AM UTC 24 Oct 12 01:24:25 AM UTC 24 452532817512 ps
T201 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.2374631421 Oct 12 01:24:12 AM UTC 24 Oct 12 01:24:27 AM UTC 24 10502400163 ps
T142 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_polled.2622037028 Oct 12 01:18:56 AM UTC 24 Oct 12 01:24:28 AM UTC 24 163413345296 ps
T395 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_alert_test.4171955748 Oct 12 01:24:26 AM UTC 24 Oct 12 01:24:28 AM UTC 24 308491906 ps
T396 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_polled_fixed.474704777 Oct 12 01:23:01 AM UTC 24 Oct 12 01:24:29 AM UTC 24 162389742809 ps
T397 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_smoke.2065501474 Oct 12 01:24:28 AM UTC 24 Oct 12 01:24:36 AM UTC 24 5519561971 ps
T207 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_clock_gating.1098708272 Oct 12 01:14:10 AM UTC 24 Oct 12 01:24:36 AM UTC 24 318717410042 ps
T136 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_interrupt.1366292755 Oct 12 01:17:52 AM UTC 24 Oct 12 01:24:36 AM UTC 24 167426441877 ps
T398 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_interrupt_fixed.3181386611 Oct 12 01:17:57 AM UTC 24 Oct 12 01:24:37 AM UTC 24 494166891935 ps
T256 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_interrupt.2542288779 Oct 12 01:23:04 AM UTC 24 Oct 12 01:24:51 AM UTC 24 163835862565 ps
T399 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_polled_fixed.3316585293 Oct 12 01:14:06 AM UTC 24 Oct 12 01:25:02 AM UTC 24 165574167427 ps
T400 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_wakeup_fixed.2280962295 Oct 12 01:19:18 AM UTC 24 Oct 12 01:25:08 AM UTC 24 412827121663 ps
T349 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_fsm_reset.2861691413 Oct 12 01:13:51 AM UTC 24 Oct 12 01:25:08 AM UTC 24 128942811107 ps
T54 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_stress_all.1533478309 Oct 12 01:14:01 AM UTC 24 Oct 12 01:25:17 AM UTC 24 125861996358 ps
T401 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_poweron_counter.4113237974 Oct 12 01:25:03 AM UTC 24 Oct 12 01:25:19 AM UTC 24 3650364549 ps
T55 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_fsm_reset.2085324205 Oct 12 01:13:59 AM UTC 24 Oct 12 01:25:19 AM UTC 24 110083185618 ps
T402 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_alert_test.239424210 Oct 12 01:25:20 AM UTC 24 Oct 12 01:25:24 AM UTC 24 470175653 ps
T56 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.3624903804 Oct 12 01:25:17 AM UTC 24 Oct 12 01:25:30 AM UTC 24 2925018836 ps
T403 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_smoke.3843864918 Oct 12 01:25:25 AM UTC 24 Oct 12 01:25:33 AM UTC 24 5800789236 ps
T404 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_lowpower_counter.2323977116 Oct 12 01:25:09 AM UTC 24 Oct 12 01:25:33 AM UTC 24 31692107894 ps
T405 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_polled_fixed.3521377567 Oct 12 01:18:56 AM UTC 24 Oct 12 01:25:34 AM UTC 24 493400186295 ps
T350 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_fsm_reset.1089769076 Oct 12 01:14:39 AM UTC 24 Oct 12 01:25:50 AM UTC 24 101875131632 ps
T137 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_both.3588193448 Oct 12 01:24:52 AM UTC 24 Oct 12 01:26:10 AM UTC 24 333029781983 ps
T143 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_wakeup.2896690027 Oct 12 01:16:38 AM UTC 24 Oct 12 01:26:34 AM UTC 24 186892704483 ps
T192 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_both.65489634 Oct 12 01:18:09 AM UTC 24 Oct 12 01:26:43 AM UTC 24 342433065810 ps
T167 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_both.519098030 Oct 12 01:20:13 AM UTC 24 Oct 12 01:26:47 AM UTC 24 515430495513 ps
T225 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_polled.3862540084 Oct 12 01:25:31 AM UTC 24 Oct 12 01:26:55 AM UTC 24 163475031009 ps
T406 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_lowpower_counter.1726298154 Oct 12 01:23:51 AM UTC 24 Oct 12 01:26:55 AM UTC 24 44498749351 ps
T407 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_poweron_counter.1202365612 Oct 12 01:26:48 AM UTC 24 Oct 12 01:26:56 AM UTC 24 4045852953 ps
T208 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_wakeup.1302542119 Oct 12 01:18:00 AM UTC 24 Oct 12 01:27:03 AM UTC 24 347354621961 ps
T364 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_fsm_reset.2695875592 Oct 12 01:18:21 AM UTC 24 Oct 12 01:27:09 AM UTC 24 99735399986 ps
T244 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_stress_all.446799079 Oct 12 01:25:19 AM UTC 24 Oct 12 01:27:10 AM UTC 24 262351556270 ps
T408 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_alert_test.91844477 Oct 12 01:27:10 AM UTC 24 Oct 12 01:27:12 AM UTC 24 386536792 ps
T217 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_wakeup.2750818573 Oct 12 01:24:37 AM UTC 24 Oct 12 01:27:20 AM UTC 24 196345066420 ps
T409 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_smoke.4082756709 Oct 12 01:27:11 AM UTC 24 Oct 12 01:27:24 AM UTC 24 5900692594 ps
T199 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_interrupt.4101661851 Oct 12 01:15:18 AM UTC 24 Oct 12 01:27:25 AM UTC 24 331031921963 ps
T179 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.2497263574 Oct 12 01:26:57 AM UTC 24 Oct 12 01:27:27 AM UTC 24 6439030875 ps
T410 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_lowpower_counter.1811894556 Oct 12 01:26:56 AM UTC 24 Oct 12 01:27:34 AM UTC 24 40420687796 ps
T144 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_stress_all.2782539721 Oct 12 01:18:27 AM UTC 24 Oct 12 01:27:42 AM UTC 24 340346501022 ps
T223 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_clock_gating.3883270240 Oct 12 01:26:35 AM UTC 24 Oct 12 01:27:47 AM UTC 24 168949955972 ps
T240 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_interrupt.1163650533 Oct 12 01:24:30 AM UTC 24 Oct 12 01:28:06 AM UTC 24 323126310416 ps
T411 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_poweron_counter.1995272959 Oct 12 01:28:07 AM UTC 24 Oct 12 01:28:20 AM UTC 24 4905467268 ps
T219 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_wakeup.1103530067 Oct 12 01:27:28 AM UTC 24 Oct 12 01:28:21 AM UTC 24 397070144777 ps
T233 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_interrupt.2857028687 Oct 12 01:27:24 AM UTC 24 Oct 12 01:28:23 AM UTC 24 163725775769 ps
T149 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_polled.210155488 Oct 12 01:15:59 AM UTC 24 Oct 12 01:28:24 AM UTC 24 323567891494 ps
T26 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.1532785143 Oct 12 01:28:23 AM UTC 24 Oct 12 01:28:34 AM UTC 24 3738604312 ps
T412 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_alert_test.3166141750 Oct 12 01:28:34 AM UTC 24 Oct 12 01:28:37 AM UTC 24 516491823 ps
T187 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_polled.1650454450 Oct 12 01:24:29 AM UTC 24 Oct 12 01:28:39 AM UTC 24 324894848910 ps
T202 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_interrupt.1608674596 Oct 12 01:21:34 AM UTC 24 Oct 12 01:28:44 AM UTC 24 166274065884 ps
T245 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_both.2999003221 Oct 12 01:14:11 AM UTC 24 Oct 12 01:28:45 AM UTC 24 326977051633 ps
T413 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_smoke.3896349544 Oct 12 01:28:38 AM UTC 24 Oct 12 01:28:47 AM UTC 24 6074063170 ps
T414 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_wakeup_fixed.4079097676 Oct 12 01:18:01 AM UTC 24 Oct 12 01:28:50 AM UTC 24 599766622133 ps
T211 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_stress_all.372169891 Oct 12 01:21:03 AM UTC 24 Oct 12 01:28:52 AM UTC 24 201595157684 ps
T155 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_stress_all.883188567 Oct 12 01:22:50 AM UTC 24 Oct 12 01:28:58 AM UTC 24 482051460165 ps
T274 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_stress_all.3759206460 Oct 12 01:27:04 AM UTC 24 Oct 12 01:29:02 AM UTC 24 163415842649 ps
T415 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_polled_fixed.3727318133 Oct 12 01:13:53 AM UTC 24 Oct 12 01:29:03 AM UTC 24 482178796451 ps
T416 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_interrupt_fixed.1208243113 Oct 12 01:21:34 AM UTC 24 Oct 12 01:29:04 AM UTC 24 165722658562 ps
T218 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_wakeup.1845032249 Oct 12 01:25:50 AM UTC 24 Oct 12 01:29:06 AM UTC 24 542441082447 ps
T417 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_polled_fixed.2770950383 Oct 12 01:27:20 AM UTC 24 Oct 12 01:29:07 AM UTC 24 164882977701 ps
T418 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_poweron_counter.3610343491 Oct 12 01:29:04 AM UTC 24 Oct 12 01:29:13 AM UTC 24 3282409896 ps
T419 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_interrupt_fixed.1685295183 Oct 12 01:24:37 AM UTC 24 Oct 12 01:29:15 AM UTC 24 325284908986 ps
T420 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_lowpower_counter.1187674377 Oct 12 01:29:05 AM UTC 24 Oct 12 01:29:17 AM UTC 24 25377690457 ps
T421 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_interrupt_fixed.2940970126 Oct 12 01:16:28 AM UTC 24 Oct 12 01:29:19 AM UTC 24 326874352815 ps
T195 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.3705796427 Oct 12 01:29:07 AM UTC 24 Oct 12 01:29:19 AM UTC 24 1573473551 ps
T422 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_alert_test.4060954646 Oct 12 01:29:16 AM UTC 24 Oct 12 01:29:20 AM UTC 24 492700428 ps
T423 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_lowpower_counter.3072612789 Oct 12 01:28:20 AM UTC 24 Oct 12 01:29:26 AM UTC 24 36536574872 ps
T424 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_polled_fixed.3206500323 Oct 12 01:15:16 AM UTC 24 Oct 12 01:29:30 AM UTC 24 328049916026 ps
T425 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_smoke.2958579684 Oct 12 01:29:18 AM UTC 24 Oct 12 01:29:33 AM UTC 24 5879311769 ps
T426 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_interrupt_fixed.1968706561 Oct 12 01:25:35 AM UTC 24 Oct 12 01:29:43 AM UTC 24 328997054516 ps
T247 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_clock_gating.741181204 Oct 12 01:22:28 AM UTC 24 Oct 12 01:29:51 AM UTC 24 332444506086 ps
T427 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_polled_fixed.536058759 Oct 12 01:24:29 AM UTC 24 Oct 12 01:29:56 AM UTC 24 486988298082 ps
T428 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_poweron_counter.996220925 Oct 12 01:29:56 AM UTC 24 Oct 12 01:30:05 AM UTC 24 2981515670 ps
T429 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_stress_all.1853352305 Oct 12 01:17:45 AM UTC 24 Oct 12 01:30:05 AM UTC 24 146482185384 ps
T430 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_fsm_reset.3992475953 Oct 12 01:24:12 AM UTC 24 Oct 12 01:30:07 AM UTC 24 91241710191 ps
T431 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_polled_fixed.1998643098 Oct 12 01:21:23 AM UTC 24 Oct 12 01:30:10 AM UTC 24 166096377210 ps
T203 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_both.727610609 Oct 12 01:22:31 AM UTC 24 Oct 12 01:30:16 AM UTC 24 334022523030 ps
T432 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_alert_test.2577186627 Oct 12 01:30:18 AM UTC 24 Oct 12 01:30:21 AM UTC 24 473070289 ps
T180 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_polled.3967716028 Oct 12 01:28:41 AM UTC 24 Oct 12 01:30:35 AM UTC 24 335785307114 ps
T433 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_fsm_reset.4279190096 Oct 12 01:22:46 AM UTC 24 Oct 12 01:30:39 AM UTC 24 129493155637 ps
T434 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_lowpower_counter.2524249568 Oct 12 01:30:05 AM UTC 24 Oct 12 01:30:45 AM UTC 24 37837820114 ps
T435 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_smoke.1928218523 Oct 12 01:30:23 AM UTC 24 Oct 12 01:30:46 AM UTC 24 6042754482 ps
T436 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_interrupt_fixed.47377717 Oct 12 01:23:11 AM UTC 24 Oct 12 01:30:50 AM UTC 24 166395138854 ps
T241 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_clock_gating.556811591 Oct 12 01:24:38 AM UTC 24 Oct 12 01:30:57 AM UTC 24 182918552568 ps
T259 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_both.3026394312 Oct 12 01:14:55 AM UTC 24 Oct 12 01:30:58 AM UTC 24 344670462456 ps
T181 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_stress_all.827163083 Oct 12 01:28:25 AM UTC 24 Oct 12 01:31:01 AM UTC 24 686510997220 ps
T313 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_polled.3372734473 Oct 12 01:23:01 AM UTC 24 Oct 12 01:31:08 AM UTC 24 164570201190 ps
T242 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_wakeup.1387511458 Oct 12 01:23:27 AM UTC 24 Oct 12 01:31:09 AM UTC 24 316300560879 ps
T200 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_both.2890147554 Oct 12 01:26:44 AM UTC 24 Oct 12 01:31:15 AM UTC 24 165434275296 ps
T363 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_fsm_reset.3355886345 Oct 12 01:25:10 AM UTC 24 Oct 12 01:31:16 AM UTC 24 70239563221 ps
T437 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_poweron_counter.3905822228 Oct 12 01:31:01 AM UTC 24 Oct 12 01:31:16 AM UTC 24 3922831937 ps
T52 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_fsm_reset.3102152596 Oct 12 01:20:29 AM UTC 24 Oct 12 01:31:24 AM UTC 24 120104551057 ps
T438 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_alert_test.41338169 Oct 12 01:31:23 AM UTC 24 Oct 12 01:31:25 AM UTC 24 422035320 ps
T257 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_both.1001836843 Oct 12 01:27:48 AM UTC 24 Oct 12 01:31:34 AM UTC 24 280996451701 ps
T27 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.4069006573 Oct 12 01:31:23 AM UTC 24 Oct 12 01:31:38 AM UTC 24 7964748642 ps
T439 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_smoke.4196580649 Oct 12 01:31:25 AM UTC 24 Oct 12 01:31:38 AM UTC 24 5980474652 ps
T177 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_polled.417865034 Oct 12 01:27:13 AM UTC 24 Oct 12 01:31:44 AM UTC 24 331447741409 ps
T220 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_clock_gating.3975531642 Oct 12 01:14:31 AM UTC 24 Oct 12 01:31:52 AM UTC 24 345161949640 ps
T265 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_both.2781291309 Oct 12 01:23:41 AM UTC 24 Oct 12 01:32:05 AM UTC 24 171705962347 ps
T226 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_stress_all.1666023766 Oct 12 01:30:12 AM UTC 24 Oct 12 01:32:08 AM UTC 24 202349195911 ps
T440 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_wakeup_fixed.990733027 Oct 12 01:27:35 AM UTC 24 Oct 12 01:32:17 AM UTC 24 406843035738 ps
T193 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_interrupt.1200529213 Oct 12 01:28:46 AM UTC 24 Oct 12 01:32:22 AM UTC 24 159865168208 ps
T266 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_wakeup.2618650104 Oct 12 01:14:28 AM UTC 24 Oct 12 01:32:22 AM UTC 24 384222928966 ps
T441 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_poweron_counter.2010568520 Oct 12 01:32:09 AM UTC 24 Oct 12 01:32:25 AM UTC 24 3431581863 ps
T231 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_clock_gating.1213180732 Oct 12 01:30:57 AM UTC 24 Oct 12 01:32:33 AM UTC 24 158414979527 ps
T442 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_polled_fixed.1774833229 Oct 12 01:30:40 AM UTC 24 Oct 12 01:32:34 AM UTC 24 326990372503 ps
T291 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_interrupt.664003990 Oct 12 01:29:22 AM UTC 24 Oct 12 01:32:38 AM UTC 24 163379685968 ps
T443 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.3915696294 Oct 12 01:32:23 AM UTC 24 Oct 12 01:32:38 AM UTC 24 3439758603 ps
T328 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_polled.324488559 Oct 12 01:31:27 AM UTC 24 Oct 12 01:32:38 AM UTC 24 158656101808 ps
T444 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_alert_test.3498577623 Oct 12 01:32:34 AM UTC 24 Oct 12 01:32:38 AM UTC 24 530661103 ps
T445 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_smoke.3750464545 Oct 12 01:32:35 AM UTC 24 Oct 12 01:32:43 AM UTC 24 5925676720 ps
T446 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_lowpower_counter.3589366814 Oct 12 01:32:18 AM UTC 24 Oct 12 01:32:57 AM UTC 24 27371283862 ps
T447 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_wakeup_fixed.2187887404 Oct 12 01:30:56 AM UTC 24 Oct 12 01:33:13 AM UTC 24 201892844629 ps
T448 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_interrupt_fixed.505208817 Oct 12 01:27:27 AM UTC 24 Oct 12 01:33:18 AM UTC 24 497235614748 ps
T449 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_lowpower_counter.2619350753 Oct 12 01:31:09 AM UTC 24 Oct 12 01:33:29 AM UTC 24 37291788535 ps
T450 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_interrupt_fixed.424782979 Oct 12 01:19:01 AM UTC 24 Oct 12 01:33:31 AM UTC 24 491057605385 ps
T451 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_poweron_counter.3601478717 Oct 12 01:33:30 AM UTC 24 Oct 12 01:33:47 AM UTC 24 3919628295 ps
T452 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_interrupt_fixed.3273695092 Oct 12 01:13:53 AM UTC 24 Oct 12 01:33:48 AM UTC 24 329228591140 ps
T168 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_clock_gating.3910804606 Oct 12 01:29:43 AM UTC 24 Oct 12 01:33:52 AM UTC 24 330330329086 ps
T453 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_lowpower_counter.196860542 Oct 12 01:33:32 AM UTC 24 Oct 12 01:33:57 AM UTC 24 36544484946 ps
T454 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_alert_test.796952299 Oct 12 01:33:58 AM UTC 24 Oct 12 01:34:02 AM UTC 24 451822499 ps
T455 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_stress_all.1153285281 Oct 12 01:31:23 AM UTC 24 Oct 12 01:34:03 AM UTC 24 52356145696 ps
T456 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.3023963792 Oct 12 01:33:48 AM UTC 24 Oct 12 01:34:18 AM UTC 24 2669138704 ps
T457 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_smoke.3639501811 Oct 12 01:34:03 AM UTC 24 Oct 12 01:34:19 AM UTC 24 5831584996 ps
T232 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_interrupt.1191159381 Oct 12 01:18:57 AM UTC 24 Oct 12 01:34:30 AM UTC 24 328392034524 ps
T355 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_fsm_reset.2196012494 Oct 12 01:17:27 AM UTC 24 Oct 12 01:34:32 AM UTC 24 111518420375 ps
T275 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_polled.831039643 Oct 12 01:30:36 AM UTC 24 Oct 12 01:34:35 AM UTC 24 324312470484 ps
T150 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_polled.2156145978 Oct 12 01:21:15 AM UTC 24 Oct 12 01:34:37 AM UTC 24 493079341995 ps
T458 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_polled_fixed.1814676155 Oct 12 01:32:39 AM UTC 24 Oct 12 01:35:05 AM UTC 24 160821716444 ps
T196 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_clock_gating.2513169892 Oct 12 01:27:43 AM UTC 24 Oct 12 01:35:06 AM UTC 24 340436348778 ps
T197 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_clock_gating.867994488 Oct 12 01:31:52 AM UTC 24 Oct 12 01:35:11 AM UTC 24 346227031050 ps
T151 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_clock_gating.3801515879 Oct 12 01:33:14 AM UTC 24 Oct 12 01:35:14 AM UTC 24 508098930125 ps
T182 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_both.972090919 Oct 12 01:29:51 AM UTC 24 Oct 12 01:35:16 AM UTC 24 524138609536 ps
T459 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_poweron_counter.2580365295 Oct 12 01:35:07 AM UTC 24 Oct 12 01:35:21 AM UTC 24 2865118970 ps
T460 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_lowpower_counter.116643972 Oct 12 01:35:11 AM UTC 24 Oct 12 01:35:28 AM UTC 24 44226464132 ps
T28 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.1886140076 Oct 12 01:35:16 AM UTC 24 Oct 12 01:35:29 AM UTC 24 4184681494 ps
T461 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_alert_test.2832709298 Oct 12 01:35:29 AM UTC 24 Oct 12 01:35:31 AM UTC 24 469223899 ps
T462 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_fsm_reset.2200529934 Oct 12 01:30:06 AM UTC 24 Oct 12 01:35:48 AM UTC 24 77827503249 ps
T463 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_wakeup.2233049009 Oct 12 01:34:33 AM UTC 24 Oct 12 01:35:49 AM UTC 24 187239724749 ps
T464 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_interrupt_fixed.4175757853 Oct 12 01:14:07 AM UTC 24 Oct 12 01:35:55 AM UTC 24 492775233181 ps
T254 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_stress_all.2432441590 Oct 12 01:33:53 AM UTC 24 Oct 12 01:35:59 AM UTC 24 195240002125 ps
T465 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_smoke.3422364275 Oct 12 01:35:31 AM UTC 24 Oct 12 01:35:59 AM UTC 24 5605623097 ps
T214 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_both.4190987306 Oct 12 01:15:28 AM UTC 24 Oct 12 01:36:11 AM UTC 24 434840024921 ps
T466 /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_interrupt_fixed.3972581892 Oct 12 01:29:27 AM UTC 24 Oct 12 01:36:16 AM UTC 24 163860939575 ps