Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23282

1

T1

20

T3

20

T4

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19782

1

T1

20

T3

20

T4

11

auto[ADC_CTRL_FILTER_COND_OUT]

3500

1

T6

4

T10

2

T14

32

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17341

1

T1

20

T3

20

T4

11

auto[1]

5941

1

T6

4

T10

5

T11

4

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19546

1

T1

20

T3

20

T4

11

auto[1]

3736

1

T6

2

T10

2

T11

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	308	1			T10	1		T13	2		T38	1
values[0]	26	1			T183	6		T184	8		T185	1
values[1]	707	1			T10	2		T12	25		T14	2
values[2]	2968	1			T15	2		T18	19		T166	2
values[3]	593	1			T10	2		T130	6		T138	18
values[4]	523	1			T14	9		T130	6		T139	1
values[5]	773	1			T37	11		T38	2		T34	1
values[6]	725	1			T38	4		T34	11		T39	1
values[7]	570	1			T16	1		T80	1		T81	9
values[8]	640	1			T13	3		T14	23		T16	1
values[9]	1254	1			T6	4		T11	4		T36	1
minimum	14195	1			T1	20		T3	20		T4	11

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	809	1			T10	2		T12	25		T14	2
values[1]	3025	1			T15	2		T18	19		T166	2
values[2]	587	1			T10	2		T130	6		T138	15
values[3]	543	1			T14	9		T38	2		T130	6
values[4]	756	1			T37	11		T38	4		T34	1
values[5]	788	1			T34	11		T39	1		T133	30
values[6]	517	1			T14	23		T16	1		T80	2
values[7]	767	1			T13	3		T16	1		T43	5
values[8]	829	1			T11	4		T36	1		T45	14
values[9]	140	1			T6	4		T17	9		T186	1
minimum	14521	1			T1	20		T3	20		T4	11

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19070

1

T1

20

T3

20

T4

11

auto[1]

4212

1

T6

1

T11

1

T12

18

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T12	19		T14	1		T45	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T10	1		T34	14		T131	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1621	1			T15	2		T18	2		T166	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T138	1		T51	1		T187	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T10	2		T130	6		T138	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T140	13		T188	11		T189	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T130	6		T190	11		T148	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T14	5		T38	1		T148	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T38	2		T34	1		T45	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T37	1		T132	1		T133	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T133	11		T134	9		T56	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T34	1		T39	1		T133	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T80	2		T81	1		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T14	12		T16	1		T176	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T13	2		T147	12		T167	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T16	1		T43	4		T191	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T11	3		T36	1		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T45	8		T176	1		T192	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T17	9		T193	1		T194	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T6	3		T186	1		T149	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14408	1			T1	20		T3	20		T4	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T195	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T12	6		T14	1		T45	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T10	1		T34	14		T131	22
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1026	1			T18	17		T175	8		T46	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T138	2		T196	12		T197	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T138	14		T131	7		T198	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T189	1		T137	9		T199	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T148	9		T200	2		T151	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T14	4		T38	1		T148	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T38	2		T45	9		T191	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T37	10		T133	6		T201	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T133	10		T134	10		T192	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T34	10		T133	8		T189	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T81	8		T138	6		T181	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T14	11		T176	3		T134	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T13	1		T167	18		T202	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T43	1		T191	10		T167	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T11	1		T137	10		T203	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T45	6		T176	4		T192	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T193	10		T204	16		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T6	1		T205	2		T164	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T6	1		T10	1		T11	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T10	1		T13	2		T38	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T183	4		T184	1		T185	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T12	19		T14	1		T45	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T10	1		T34	14		T131	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1600	1			T15	2		T18	2		T166	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T28	2		T153	12		T206	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T10	2		T130	6		T138	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T138	1		T140	13		T188	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T130	6		T139	1		T198	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T14	5		T148	10		T207	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T34	1		T45	8		T191	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T37	1		T38	1		T132	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T38	2		T133	11		T147	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T34	1		T39	1		T133	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T80	1		T81	1		T143	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T16	1		T134	3		T208	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T13	2		T80	1		T138	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T14	12		T16	1		T43	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T11	3		T36	1		T17	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	428	1			T6	3		T45	8		T186	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14090	1			T1	20		T3	20		T4	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T183	2		T184	7		T209	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T12	6		T14	1		T45	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T10	1		T34	14		T131	22
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1011	1			T18	17		T175	8		T46	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T28	1		T206	10		T210	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T138	14		T131	7		T176	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T138	2		T189	1		T137	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T198	18		T211	9		T151	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T14	4		T148	9		T207	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T45	9		T191	11		T148	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T37	10		T38	1		T201	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T38	2		T133	10		T134	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T34	10		T133	14		T189	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T81	8		T212	9		T213	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T134	2		T168	14		T214	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T13	1		T138	6		T167	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T14	11		T43	1		T176	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T11	1		T137	10		T202	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T6	1		T45	6		T191	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T6	1		T10	1		T11	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T12	7		T14	2		T45	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T10	2		T34	15		T131	23
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1354	1			T15	2		T18	19		T166	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T138	3		T51	1		T187	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T10	2		T130	1		T138	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T140	1		T188	1		T189	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T130	1		T190	1		T148	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T14	5		T38	2		T148	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T38	4		T34	1		T45	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T37	11		T132	1		T133	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T133	11		T134	11		T56	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T34	11		T39	1		T133	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T80	2		T81	9		T138	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T14	12		T16	1		T176	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T13	2		T147	1		T167	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T16	1		T43	4		T191	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T11	3		T36	1		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T45	7		T176	5		T192	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T17	1		T193	11		T194	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T6	3		T186	1		T149	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14511	1			T1	20		T3	20		T4	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T195	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T12	18		T45	13		T207	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T34	13		T131	18		T215	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1293	1			T46	7		T154	18		T216	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T196	17		T197	10		T28	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T130	5		T131	12		T198	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T140	12		T188	10		T137	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T130	5		T190	10		T148	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T14	4		T148	9		T207	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T45	7		T147	9		T141	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T133	2		T140	13		T201	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T133	10		T134	8		T192	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T189	5		T167	24		T208	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T143	7		T217	2		T218	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T14	11		T134	2		T218	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T13	1		T147	11		T167	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T43	1		T167	14		T219	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T11	1		T137	12		T203	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T45	7		T192	2		T220	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T17	8		T204	5		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T6	1		T205	2		T221	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T222	2		T204	7		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	8	40	83.33	8

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T10	1		T13	2		T38	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T183	4		T184	8		T185	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T12	7		T14	2		T45	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T10	2		T34	15		T131	23
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1336	1			T15	2		T18	19		T166	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T28	2		T153	1		T206	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T10	2		T130	1		T138	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T138	3		T140	1		T188	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T130	1		T139	1		T198	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T14	5		T148	10		T207	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T34	1		T45	10		T191	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T37	11		T38	2		T132	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T38	4		T133	11		T147	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T34	11		T39	1		T133	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T80	1		T81	9		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T16	1		T134	3		T208	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T13	2		T80	1		T138	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T14	12		T16	1		T43	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T11	3		T36	1		T17	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	377	1			T6	3		T45	7		T186	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14195	1			T1	20		T3	20		T4	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T183	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T12	18		T45	13		T207	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T34	13		T131	18		T215	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1275	1			T46	7		T154	18		T216	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T28	1		T153	11		T206	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T130	5		T131	12		T25	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T140	12		T188	10		T137	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T130	5		T198	16		T190	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T14	4		T148	9		T207	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T45	7		T148	5		T141	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T201	1		T223	10		T155	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T133	10		T147	9		T134	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T133	2		T140	13		T189	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T143	7		T217	2		T218	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T134	2		T208	6		T218	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T13	1		T147	11		T167	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T14	11		T43	1		T27	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T11	1		T17	8		T137	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	366	1			T6	1		T45	7		T192	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19070

1

T1

20

T3

20

T4

11

auto[1]

auto[0]

4212

1

T6

1

T11

1

T12

18

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23282

1

T1

20

T3

20

T4

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19953

1

T1

20

T3

20

T4

11

auto[ADC_CTRL_FILTER_COND_OUT]

3329

1

T6

4

T11

4

T13

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17611

1

T1

20

T3

20

T4

11

auto[1]

5671

1

T11

4

T12

25

T13

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19546

1

T1

20

T3

20

T4

11

auto[1]

3736

1

T6

2

T10

2

T11

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	1	1			T224	1		-	-		-	-
values[0]	104	1			T138	15		T137	21		T218	12
values[1]	420	1			T10	2		T11	4		T38	2
values[2]	527	1			T37	11		T44	1		T134	19
values[3]	782	1			T10	2		T34	1		T45	39
values[4]	789	1			T13	3		T14	9		T38	4
values[5]	3107	1			T12	25		T14	2		T15	2
values[6]	671	1			T17	9		T147	10		T140	14
values[7]	734	1			T6	4		T14	23		T130	6
values[8]	664	1			T16	1		T34	28		T198	35
values[9]	981	1			T36	1		T16	1		T81	9
minimum	14502	1			T1	20		T3	20		T4	11

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	716	1			T11	4		T38	2		T34	11
values[1]	467	1			T10	4		T37	11		T133	21
values[2]	925	1			T13	3		T14	9		T38	4
values[3]	2933	1			T12	25		T15	2		T18	19
values[4]	815	1			T14	2		T17	9		T45	17
values[5]	771	1			T14	23		T130	6		T147	12
values[6]	667	1			T6	4		T34	28		T198	35
values[7]	586	1			T16	1		T131	41		T25	3
values[8]	744	1			T36	1		T16	1		T81	9
values[9]	156	1			T131	20		T155	21		T153	1
minimum	14502	1			T1	20		T3	20		T4	11

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19070

1

T1

20

T3

20

T4

11

auto[1]

4212

1

T6

1

T11

1

T12

18

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T38	1		T34	1		T138	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T11	3		T132	1		T130	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T10	3		T37	1		T133	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T215	13		T51	1		T225	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T45	14		T39	1		T139	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T13	2		T14	5		T38	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1592	1			T12	19		T15	2		T18	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T80	1		T191	1		T192	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T17	9		T147	10		T190	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T14	1		T45	8		T186	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T14	12		T130	6		T147	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T140	14		T136	1		T192	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T34	14		T198	17		T189	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T6	3		T140	1		T56	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T142	1		T207	5		T226	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T16	1		T131	19		T25	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T36	1		T16	1		T81	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T176	1		T190	9		T208	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T227	1		T228	5		T221	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T131	13		T155	12		T153	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14397	1			T1	20		T3	20		T4	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T38	1		T34	10		T138	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T11	1		T138	14		T202	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T10	1		T37	10		T133	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T215	8		T229	10		T230	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T45	11		T191	11		T176	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T13	1		T14	4		T38	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	921	1			T12	6		T18	17		T175	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T191	10		T192	2		T199	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T215	13		T181	17		T231	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T14	1		T45	9		T176	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T14	11		T168	14		T232	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T136	7		T192	11		T200	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T34	14		T198	18		T189	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T6	1		T203	2		T193	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T207	13		T197	3		T214	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T131	22		T25	1		T167	22
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T81	8		T46	9		T138	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T176	5		T144	6		T233	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T227	6		T234	15		T235	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T131	7		T155	9		T236	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T6	1		T10	1		T11	1