Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23282

1

T1

20

T3

20

T4

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19774

1

T1

20

T3

20

T4

11

auto[ADC_CTRL_FILTER_COND_OUT]

3508

1

T10

2

T11

4

T12

25

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17433

1

T1

20

T3

20

T4

11

auto[1]

5849

1

T10

2

T11

4

T12

25

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19546

1

T1

20

T3

20

T4

11

auto[1]

3736

1

T6

2

T10

2

T11

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	246	1			T140	1		T134	19		T144	10
values[0]	10	1			T245	10		-	-		-	-
values[1]	806	1			T10	2		T34	11		T81	9
values[2]	3131	1			T13	3		T15	2		T18	19
values[3]	733	1			T140	27		T188	11		T190	11
values[4]	505	1			T12	25		T37	11		T38	2
values[5]	608	1			T16	2		T80	1		T39	1
values[6]	604	1			T14	9		T45	25		T198	35
values[7]	577	1			T6	4		T11	4		T14	23
values[8]	520	1			T10	2		T14	2		T36	1
values[9]	1040	1			T34	28		T45	17		T138	7
minimum	14502	1			T1	20		T3	20		T4	11

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	632	1			T34	11		T186	1		T133	9
values[1]	3188	1			T13	3		T15	2		T18	19
values[2]	635	1			T12	25		T38	2		T140	27
values[3]	572	1			T16	1		T37	11		T34	1
values[4]	586	1			T16	1		T80	1		T39	1
values[5]	569	1			T14	9		T45	25		T147	10
values[6]	526	1			T6	4		T11	4		T14	23
values[7]	579	1			T10	2		T14	2		T36	1
values[8]	1025	1			T34	28		T45	17		T139	1
values[9]	113	1			T138	7		T223	14		T218	12
minimum	14857	1			T1	20		T3	20		T4	11

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19070

1

T1

20

T3

20

T4

11

auto[1]

4212

1

T6

1

T11

1

T12

18

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T25	2		T192	3		T208	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T34	1		T186	1		T133	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1659	1			T13	2		T15	2		T18	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T190	11		T215	26		T51	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T140	14		T141	12		T240	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T12	19		T38	1		T140	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T139	1		T133	11		T225	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T16	1		T37	1		T34	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T16	1		T80	1		T39	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T198	17		T202	1		T232	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T45	14		T134	3		T190	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T14	5		T147	10		T258	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T6	3		T130	6		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T11	3		T14	12		T46	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T10	2		T14	1		T17	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T36	1		T38	2		T45	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T34	14		T144	4		T203	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	366	1			T45	8		T139	1		T131	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T138	1		T266	4		T271	22
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T223	11		T218	12		T150	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14461	1			T1	20		T3	20		T4	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T10	1		T81	1		T130	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T25	1		T192	2		T245	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T34	10		T133	6		T201	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	983	1			T13	1		T18	17		T175	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T215	21		T51	6		T207	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T141	10		T211	9		T155	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T12	6		T38	1		T256	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T133	10		T199	2		T99	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T37	10		T131	22		T133	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T148	9		T197	12		T152	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T198	18		T202	14		T232	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T45	11		T134	2		T244	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T14	4		T258	7		T137	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T6	1		T138	14		T189	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T11	1		T14	11		T46	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T14	1		T176	4		T233	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T38	2		T45	6		T191	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T34	14		T144	6		T203	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T45	9		T131	7		T134	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T138	6		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T223	3		T283	12		T319	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T6	1		T10	1		T11	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T10	1		T81	8		T138	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T144	4		T320	1		T212	9
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T140	1		T134	9		T197	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T245	4		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T25	2		T189	6		T208	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T10	1		T34	1		T81	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1695	1			T13	2		T15	2		T18	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T215	26		T51	1		T201	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T140	14		T141	12		T240	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T140	13		T188	11		T190	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T139	1		T133	11		T225	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T12	19		T37	1		T38	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T16	1		T80	1		T39	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T16	1		T131	19		T176	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T45	14		T147	12		T134	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T14	5		T198	17		T147	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T6	3		T138	1		T189	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T11	3		T14	12		T46	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T10	2		T14	1		T17	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T36	1		T38	2		T45	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T34	14		T138	1		T203	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	371	1			T45	8		T139	1		T131	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14397	1			T1	20		T3	20		T4	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T144	6		T320	11		T212	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T134	10		T197	3		T169	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T245	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T25	1		T189	4		T203	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T10	1		T34	10		T81	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1005	1			T13	1		T18	17		T175	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T215	21		T51	6		T201	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T141	10		T321	9		T322	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T256	13		T181	12		T232	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T133	10		T211	9		T155	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T12	6		T37	10		T38	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T199	2		T197	12		T152	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T131	22		T176	3		T202	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T45	11		T134	2		T148	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T14	4		T198	18		T258	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T6	1		T138	14		T189	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T11	1		T14	11		T46	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T14	1		T176	4		T136	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T38	2		T45	6		T191	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T34	14		T138	6		T203	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T45	9		T131	7		T167	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T6	1		T10	1		T11	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T25	2		T192	3		T208	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T34	11		T186	1		T133	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1317	1			T13	2		T15	2		T18	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T190	1		T215	23		T51	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T140	1		T141	11		T240	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T12	7		T38	2		T140	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T139	1		T133	11		T225	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T16	1		T37	11		T34	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T16	1		T80	1		T39	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T198	19		T202	15		T232	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T45	12		T134	3		T190	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T14	5		T147	1		T258	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T6	3		T130	1		T138	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T11	3		T14	12		T46	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T10	2		T14	2		T17	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T36	1		T38	4		T45	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T34	15		T144	7		T203	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T45	10		T139	1		T131	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T138	7		T266	1		T271	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T223	4		T218	1		T150	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14573	1			T1	20		T3	20		T4	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T10	2		T81	9		T130	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T25	1		T192	2		T208	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T133	2		T201	1		T259	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1325	1			T13	1		T154	18		T216	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T190	10		T215	24		T207	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T140	13		T141	11		T155	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T12	18		T140	12		T188	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T133	10		T99	15		T103	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T131	18		T148	9		T167	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T147	11		T148	5		T143	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T198	16		T262	12		T210	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T45	13		T134	2		T190	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T14	4		T147	9		T137	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T6	1		T130	5		T167	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T11	1		T14	11		T46	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T17	8		T181	9		T266	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T45	7		T220	16		T93	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T34	13		T144	3		T203	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	321	1			T45	7		T131	12		T134	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T266	3		T271	21		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T223	10		T218	11		T283	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T189	5		T245	3		T323	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T130	5		T192	9		T181	15

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T144	7		T320	12		T212	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T140	1		T134	11		T197	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T245	7		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T25	2		T189	5		T208	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T10	2		T34	11		T81	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1341	1			T13	2		T15	2		T18	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T215	23		T51	7		T201	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T140	1		T141	11		T240	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T140	1		T188	1		T190	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T139	1		T133	11		T225	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T12	7		T37	11		T38	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T16	1		T80	1		T39	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T16	1		T131	23		T176	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T45	12		T147	1		T134	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T14	5		T198	19		T147	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T6	3		T138	15		T189	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T11	3		T14	12		T46	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T10	2		T14	2		T17	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T36	1		T38	4		T45	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T34	15		T138	7		T203	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T45	10		T139	1		T131	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14502	1			T1	20		T3	20		T4	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T144	3		T212	8		T324	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T134	8		T197	1		T276	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T245	3		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T25	1		T189	5		T208	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T130	5		T133	2		T192	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1359	1			T13	1		T154	18		T216	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T215	24		T201	1		T207	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T140	13		T141	11		T242	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T140	12		T188	10		T190	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T133	10		T155	11		T247	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T12	18		T148	9		T167	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T143	7		T168	7		T197	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T131	18		T247	11		T103	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T45	13		T147	11		T134	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T14	4		T198	16		T147	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T6	1		T167	12		T217	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T11	1		T14	11		T46	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T17	8		T130	5		T266	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T45	7		T220	16		T93	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T34	13		T203	4		T181	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T45	7		T131	12		T167	24

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19070

1

T1

20

T3

20

T4

11

auto[1]

auto[0]

4212

1

T6

1

T11

1

T12

18