Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23282

1

T1

20

T3

20

T4

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19899

1

T1

20

T3

20

T4

11

auto[ADC_CTRL_FILTER_COND_OUT]

3383

1

T6

4

T10

2

T11

4

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17482

1

T1

20

T3

20

T4

11

auto[1]

5800

1

T10

2

T11

4

T12

25

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19546

1

T1

20

T3

20

T4

11

auto[1]

3736

1

T6

2

T10

2

T11

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	318	1			T10	2		T186	1		T191	23
values[0]	4	1			T297	1		T303	3		-	-
values[1]	563	1			T13	3		T132	1		T139	1
values[2]	669	1			T6	4		T14	32		T17	9
values[3]	820	1			T14	2		T34	11		T45	39
values[4]	563	1			T16	1		T38	2		T45	17
values[5]	603	1			T10	2		T12	25		T37	11
values[6]	839	1			T80	1		T130	6		T199	3
values[7]	522	1			T36	1		T16	1		T38	4
values[8]	715	1			T11	4		T34	29		T138	7
values[9]	3164	1			T15	2		T18	19		T81	9
minimum	14502	1			T1	20		T3	20		T4	11

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	555	1			T14	9		T139	1		T140	27
values[1]	738	1			T6	4		T14	25		T17	9
values[2]	720	1			T16	1		T38	2		T34	11
values[3]	696	1			T45	17		T131	41		T133	9
values[4]	621	1			T10	2		T12	25		T37	11
values[5]	685	1			T36	1		T16	1		T80	1
values[6]	2845	1			T11	4		T15	2		T18	19
values[7]	766	1			T34	1		T138	7		T133	9
values[8]	885	1			T10	2		T81	9		T186	1
values[9]	142	1			T39	1		T191	12		T192	5
minimum	14629	1			T1	20		T3	20		T4	11

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19070

1

T1

20

T3

20

T4

11

auto[1]

4212

1

T6

1

T11

1

T12

18

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T153	12		T65	2		T262	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T14	5		T139	1		T140	27
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T14	1		T17	9		T80	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T6	3		T14	12		T140	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T45	14		T258	1		T188	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T16	1		T38	1		T34	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T45	8		T207	5		T240	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T131	19		T133	3		T147	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T10	1		T37	1		T56	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T12	19		T136	1		T196	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T36	1		T16	1		T130	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T80	1		T190	9		T199	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1544	1			T15	2		T18	2		T38	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T11	3		T130	6		T138	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T138	1		T148	6		T215	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T34	1		T133	1		T189	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T147	12		T176	1		T219	22
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T10	2		T81	1		T186	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T39	1		T191	1		T226	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T192	3		T155	6		T180	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14433	1			T1	20		T3	20		T4	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T132	1		T265	1		T222	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T262	19		T298	1		T103	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T14	4		T134	10		T203	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T14	1		T45	6		T46	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T6	1		T14	11		T176	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T45	11		T258	7		T215	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T38	1		T34	10		T43	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T45	9		T207	13		T240	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T131	22		T133	6		T220	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T10	1		T37	10		T193	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T12	6		T136	7		T196	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T207	11		T144	6		T223	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T199	2		T155	9		T259	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	931	1			T18	17		T38	2		T34	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T11	1		T138	2		T133	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T138	6		T148	9		T215	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T133	8		T189	1		T201	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T176	5		T211	9		T203	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T81	8		T138	14		T191	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T191	11		T278	13		T294	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T192	2		T155	5		T196	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T6	1		T10	1		T11	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T265	11		T237	9		T294	5

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T191	1		T218	21		T203	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T10	2		T186	1		T191	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T297	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T303	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T13	2		T187	1		T274	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T132	1		T139	1		T140	27
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T17	9		T80	1		T46	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T6	3		T14	17		T140	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T14	1		T45	22		T188	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T34	1		T43	4		T256	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T45	8		T258	1		T207	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T16	1		T38	1		T147	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T10	1		T37	1		T56	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T12	19		T131	19		T133	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T130	6		T144	4		T223	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T80	1		T199	1		T155	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T36	1		T16	1		T38	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T130	6		T138	1		T133	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T34	14		T138	1		T148	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T11	3		T34	1		T133	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1688	1			T15	2		T18	2		T166	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T81	1		T138	1		T135	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14397	1			T1	20		T3	20		T4	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T191	11		T203	2		T206	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T191	10		T155	5		T282	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T303	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T13	1		T262	19		T298	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T134	10		T241	10		T265	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T46	9		T131	7		T148	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T6	1		T14	15		T176	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T14	1		T45	17		T215	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T34	10		T43	1		T256	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T45	9		T258	7		T207	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T38	1		T304	15		T261	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T10	1		T37	10		T245	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T12	6		T131	22		T133	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T144	6		T223	3		T197	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T199	2		T155	9		T259	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T38	2		T198	18		T176	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T138	2		T133	10		T141	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T34	14		T138	6		T148	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T11	1		T133	8		T189	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1022	1			T18	17		T175	8		T176	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T81	8		T138	14		T192	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T6	1		T10	1		T11	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T153	1		T65	2		T262	20
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T14	5		T139	1		T140	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T14	2		T17	1		T80	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T6	3		T14	12		T140	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T45	12		T258	8		T188	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T16	1		T38	2		T34	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T45	10		T207	14		T240	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T131	23		T133	7		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T10	2		T37	11		T56	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T12	7		T136	8		T196	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T36	1		T16	1		T130	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T80	1		T190	1		T199	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1251	1			T15	2		T18	19		T38	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T11	3		T130	1		T138	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T138	7		T148	10		T215	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T34	1		T133	9		T189	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T147	1		T176	6		T219	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T10	2		T81	9		T186	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T39	1		T191	12		T226	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T192	3		T155	6		T180	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14539	1			T1	20		T3	20		T4	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T132	1		T265	12		T222	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T153	11		T262	12		T103	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T14	4		T140	25		T134	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T17	8		T45	7		T46	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T6	1		T14	11		T143	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T45	13		T188	10		T215	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T43	1		T259	13		T260	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T45	7		T207	4		T245	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T131	18		T133	2		T147	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T325	13		T283	2		T270	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T12	18		T196	5		T151	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T130	5		T207	11		T144	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T190	8		T155	11		T259	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1224	1			T34	13		T154	18		T216	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T11	1		T130	5		T133	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T148	5		T215	12		T244	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T201	1		T192	9		T167	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T147	11		T219	20		T218	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T167	14		T208	6		T217	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T294	11		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T192	2		T155	5		T196	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T13	1		T287	17		T326	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T222	2		T237	7		T294	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T191	12		T218	2		T203	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T10	2		T186	1		T191	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T297	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T303	3		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T13	2		T187	1		T274	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T132	1		T139	1		T140	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T17	1		T80	1		T46	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T6	3		T14	17		T140	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T14	2		T45	19		T188	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T34	11		T43	4		T256	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T45	10		T258	8		T207	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T16	1		T38	2		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T10	2		T37	11		T56	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T12	7		T131	23		T133	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T130	1		T144	7		T223	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T80	1		T199	3		T155	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T36	1		T16	1		T38	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T130	1		T138	3		T133	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T34	15		T138	7		T148	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T11	3		T34	1		T133	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1365	1			T15	2		T18	19		T166	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T81	9		T138	15		T135	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14502	1			T1	20		T3	20		T4	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T218	19		T203	4		T206	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T155	5		T282	11		T163	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T13	1		T153	11		T262	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T140	25		T134	8		T241	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T17	8		T46	7		T131	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T6	1		T14	15		T143	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T45	20		T188	10		T215	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T43	1		T167	24		T259	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T45	7		T207	4		T268	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T147	9		T247	3		T304	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T245	12		T93	14		T268	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T12	18		T131	18		T133	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T130	5		T144	3		T223	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T155	11		T259	9		T276	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T198	16		T134	2		T190	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T130	5		T133	10		T190	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T34	13		T148	5		T244	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T11	1		T201	1		T192	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1345	1			T154	18		T216	16		T146	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T192	2		T167	14		T208	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19070

1

T1

20

T3

20

T4

11

auto[1]

auto[0]

4212

1

T6

1

T11

1

T12

18