Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23282

1

T1

20

T3

20

T4

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20051

1

T1

20

T3

20

T4

11

auto[ADC_CTRL_FILTER_COND_OUT]

3231

1

T6

4

T11

4

T14

23

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17152

1

T1

20

T3

20

T4

11

auto[1]

6130

1

T6

4

T10

5

T12

25

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19546

1

T1

20

T3

20

T4

11

auto[1]

3736

1

T6

2

T10

2

T11

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	433	1			T6	4		T10	1		T13	2
values[0]	8	1			T183	6		T289	1		T185	1
values[1]	772	1			T10	2		T12	25		T14	2
values[2]	2887	1			T15	2		T18	19		T166	2
values[3]	601	1			T10	2		T130	6		T138	15
values[4]	601	1			T14	9		T130	6		T139	1
values[5]	748	1			T37	11		T38	2		T34	1
values[6]	605	1			T38	4		T34	11		T39	1
values[7]	637	1			T16	1		T80	1		T81	9
values[8]	705	1			T13	3		T14	23		T16	1
values[9]	1090	1			T11	4		T36	1		T17	9
minimum	14195	1			T1	20		T3	20		T4	11

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	702	1			T10	2		T14	2		T34	28
values[1]	2958	1			T15	2		T18	19		T166	2
values[2]	627	1			T10	2		T14	9		T130	6
values[3]	536	1			T130	6		T190	11		T148	34
values[4]	807	1			T37	11		T38	6		T34	1
values[5]	641	1			T34	11		T39	1		T133	30
values[6]	659	1			T14	23		T16	1		T80	1
values[7]	660	1			T13	3		T16	1		T80	1
values[8]	909	1			T11	4		T36	1		T17	9
values[9]	119	1			T6	4		T149	1		T193	11
minimum	14664	1			T1	20		T3	20		T4	11

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19070

1

T1

20

T3

20

T4

11

auto[1]

4212

1

T6

1

T11

1

T12

18

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T10	1		T14	1		T45	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T34	14		T131	19		T140	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1623	1			T15	2		T18	2		T166	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T138	1		T51	2		T245	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T10	2		T14	5		T138	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T130	6		T140	13		T188	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T130	6		T190	11		T148	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T148	10		T207	12		T155	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T37	1		T38	2		T34	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T38	1		T132	1		T140	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T133	11		T134	9		T189	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T34	1		T39	1		T133	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T80	1		T138	1		T143	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T14	12		T16	1		T81	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T13	2		T147	12		T191	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T16	1		T80	1		T43	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T17	9		T176	1		T137	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T11	3		T36	1		T45	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T193	1		T194	1		T331	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T6	3		T149	1		T150	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14444	1			T1	20		T3	20		T4	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T240	1		T247	12		T178	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T10	1		T14	1		T45	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T34	14		T131	22		T215	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1006	1			T18	17		T175	8		T46	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T138	2		T51	6		T245	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T14	4		T138	14		T131	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T189	1		T199	2		T245	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T148	9		T257	10		T152	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T148	9		T207	11		T155	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T37	10		T38	2		T45	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T38	1		T201	1		T259	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T133	10		T134	10		T189	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T34	10		T133	8		T167	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T138	6		T181	29		T278	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T14	11		T81	8		T176	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T13	1		T191	10		T167	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T43	1		T163	9		T158	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T176	4		T137	10		T167	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T11	1		T45	6		T192	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T193	10		T331	9		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T6	1		T164	1		T234	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T6	1		T10	1		T11	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T237	9		T229	10		T279	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	368	1			T10	1		T13	2		T38	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T6	3		T139	1		T150	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T183	4		T185	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T289	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T10	1		T12	19		T14	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T34	14		T131	19		T140	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1611	1			T15	2		T18	2		T166	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T138	1		T51	1		T245	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T10	2		T138	1		T131	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T130	6		T140	13		T188	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T14	5		T130	6		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T190	9		T148	10		T207	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T37	1		T34	1		T45	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T38	1		T132	1		T201	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T38	2		T133	14		T147	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T34	1		T39	1		T133	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T80	1		T56	2		T143	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T16	1		T81	1		T134	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T13	2		T138	1		T147	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T14	12		T16	1		T80	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T17	9		T191	1		T167	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	372	1			T11	3		T36	1		T45	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14090	1			T1	20		T3	20		T4	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T176	4		T137	10		T185	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T6	1		T197	3		T332	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T183	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T10	1		T12	6		T14	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T34	14		T131	22		T215	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	978	1			T18	17		T175	8		T46	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T138	2		T51	6		T245	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T138	14		T131	7		T176	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T189	1		T199	2		T245	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T14	4		T198	18		T148	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T148	9		T207	11		T155	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T37	10		T45	9		T191	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T38	1		T201	1		T259	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T38	2		T133	16		T134	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T34	10		T133	8		T232	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T212	9		T282	11		T169	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T81	8		T134	2		T167	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T13	1		T138	6		T167	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T14	11		T43	1		T176	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T191	10		T167	10		T202	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T11	1		T45	6		T192	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T6	1		T10	1		T11	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T10	2		T14	2		T45	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T34	15		T131	23		T140	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1336	1			T15	2		T18	19		T166	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T138	3		T51	8		T245	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T10	2		T14	5		T138	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T130	1		T140	1		T188	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T130	1		T190	1		T148	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T148	10		T207	12		T155	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T37	11		T38	4		T34	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T38	2		T132	1		T140	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T133	11		T134	11		T189	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T34	11		T39	1		T133	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T80	1		T138	7		T143	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T14	12		T16	1		T81	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T13	2		T147	1		T191	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T16	1		T80	1		T43	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T17	1		T176	5		T137	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T11	3		T36	1		T45	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T193	11		T194	1		T331	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T6	3		T149	1		T150	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14539	1			T1	20		T3	20		T4	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T240	1		T247	1		T178	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T45	13		T207	4		T203	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T34	13		T131	18		T215	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1293	1			T46	7		T154	18		T216	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T245	3		T182	15		T210	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T14	4		T131	12		T198	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T130	5		T140	12		T188	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T130	5		T190	10		T148	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T148	9		T207	11		T155	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T45	7		T133	2		T147	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T140	13		T201	1		T259	22
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T133	10		T134	8		T189	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T167	24		T208	6		T266	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T143	7		T217	2		T218	27
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T14	11		T134	2		T27	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T13	1		T147	11		T167	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T43	1		T260	11		T333	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T17	8		T137	12		T167	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T11	1		T45	7		T192	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T331	13		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T6	1		T221	17		T334	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T12	18		T222	2		T335	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T247	11		T178	7		T237	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	355	1			T10	1		T13	2		T38	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T6	3		T139	1		T150	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T183	4		T185	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T289	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T10	2		T12	7		T14	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T34	15		T131	23		T140	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1308	1			T15	2		T18	19		T166	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T138	3		T51	7		T245	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T10	2		T138	15		T131	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T130	1		T140	1		T188	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T14	5		T130	1		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T190	1		T148	10		T207	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T37	11		T34	1		T45	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T38	2		T132	1		T201	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T38	4		T133	18		T147	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T34	11		T39	1		T133	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T80	1		T56	2		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T16	1		T81	9		T134	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T13	2		T138	7		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T14	12		T16	1		T80	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T17	1		T191	11		T167	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T11	3		T36	1		T45	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14195	1			T1	20		T3	20		T4	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T137	12		T331	13		T336	22
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T6	1		T197	1		T334	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T183	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T12	18		T45	13		T207	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T34	13		T131	18		T215	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1281	1			T46	7		T154	18		T216	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T245	3		T242	3		T210	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T131	12		T25	1		T155	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T130	5		T140	12		T188	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T14	4		T130	5		T198	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T190	8		T148	9		T207	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T45	7		T141	11		T223	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T201	1		T259	22		T200	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T133	12		T147	9		T134	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T140	13		T266	3		T196	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T143	7		T217	2		T218	27
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T134	2		T167	24		T208	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T13	1		T147	11		T167	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T14	11		T43	1		T27	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T17	8		T167	14		T219	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	321	1			T11	1		T45	7		T192	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19070

1

T1

20

T3

20

T4

11

auto[1]

auto[0]

4212

1

T6

1

T11

1

T12

18