Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23282

1

T1

20

T3

20

T4

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

17573

1

T1

20

T3

20

T4

11

auto[ADC_CTRL_FILTER_COND_OUT]

5709

1

T6

4

T14

32

T36

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17233

1

T1

20

T3

20

T4

11

auto[1]

6049

1

T11

4

T14

23

T15

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19546

1

T1

20

T3

20

T4

11

auto[1]

3736

1

T6

2

T10

2

T11

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	237	1			T131	41		T44	1		T25	3
values[0]	28	1			T215	21		T187	1		T314	6
values[1]	785	1			T6	4		T38	4		T34	1
values[2]	549	1			T10	2		T14	23		T138	3
values[3]	665	1			T36	1		T17	9		T39	1
values[4]	757	1			T37	11		T132	1		T45	17
values[5]	465	1			T34	28		T80	1		T191	12
values[6]	608	1			T14	9		T81	9		T139	1
values[7]	635	1			T10	2		T16	1		T45	25
values[8]	682	1			T11	4		T12	25		T13	3
values[9]	3369	1			T14	2		T15	2		T16	1
minimum	14502	1			T1	20		T3	20		T4	11

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	857	1			T38	4		T34	1		T45	14
values[1]	2690	1			T10	2		T14	23		T36	1
values[2]	679	1			T17	9		T132	1		T45	17
values[3]	701	1			T37	11		T80	1		T131	20
values[4]	573	1			T14	9		T34	28		T133	9
values[5]	537	1			T16	1		T81	9		T139	1
values[6]	679	1			T10	2		T11	4		T38	2
values[7]	710	1			T12	25		T13	3		T46	17
values[8]	1043	1			T14	2		T16	1		T34	11
values[9]	143	1			T137	23		T339	8		T296	15
minimum	14670	1			T1	20		T3	20		T4	11

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19070

1

T1

20

T3

20

T4

11

auto[1]

4212

1

T6

1

T11

1

T12

18

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	344	1			T38	2		T133	3		T189	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T34	1		T45	8		T147	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T10	2		T138	1		T43	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1561	1			T14	12		T36	1		T15	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T132	1		T139	1		T176	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T17	9		T45	8		T39	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T37	1		T131	13		T137	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T80	1		T191	1		T188	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T34	14		T179	1		T144	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T14	5		T133	1		T143	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T258	1		T167	15		T247	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T16	1		T81	1		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T10	1		T11	3		T38	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T45	14		T133	11		T256	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T12	19		T13	2		T46	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T198	17		T190	9		T218	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T14	1		T16	1		T130	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	336	1			T34	1		T186	1		T131	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T339	8		T204	8		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T137	13		T296	15		T294	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14415	1			T1	20		T3	20		T4	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T6	3		T80	1		T215	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T38	2		T133	6		T189	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T45	6		T244	7		T199	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T138	2		T43	1		T176	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	936	1			T14	11		T18	17		T175	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T176	5		T215	13		T136	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T45	9		T148	9		T167	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T37	10		T131	7		T137	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T191	11		T245	14		T211	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T34	14		T144	6		T181	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T14	4		T133	8		T167	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T258	7		T167	10		T268	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T81	8		T141	10		T202	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T10	1		T11	1		T38	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T45	11		T133	10		T256	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T12	6		T13	1		T46	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T198	18		T262	19		T320	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T14	1		T176	3		T134	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T34	10		T131	22		T207	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T204	7		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T137	10		T294	14		T340	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T6	1		T10	1		T11	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T6	1		T215	8		T201	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T25	2		T218	4		T203	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T131	19		T44	1		T142	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T314	6		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T215	13		T187	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T38	2		T138	1		T133	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T6	3		T34	1		T80	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T10	2		T138	1		T43	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T14	12		T167	25		T149	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T176	1		T215	13		T136	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T36	1		T17	9		T39	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T37	1		T132	1		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T45	8		T188	11		T148	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T34	14		T179	1		T144	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T80	1		T191	1		T240	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T258	1		T167	15		T247	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T14	5		T81	1		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T10	1		T191	1		T148	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T16	1		T45	14		T133	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T11	3		T12	19		T13	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T190	9		T256	1		T313	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T14	1		T16	1		T130	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1786	1			T15	2		T18	2		T34	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14397	1			T1	20		T3	20		T4	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T25	1		T203	2		T193	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T131	22		T210	16		T341	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T215	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T38	2		T138	6		T133	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T6	1		T45	6		T201	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T138	2		T43	1		T189	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T14	11		T167	12		T259	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T176	4		T215	13		T136	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T245	6		T214	14		T213	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T37	10		T131	7		T176	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T45	9		T148	9		T245	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T34	14		T144	6		T265	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T191	11		T240	16		T298	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T258	7		T167	10		T181	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T14	4		T81	8		T133	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T10	1		T191	10		T148	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T45	11		T133	10		T220	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T11	1		T12	6		T13	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T256	13		T262	19		T268	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T14	1		T138	14		T176	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1130	1			T18	17		T34	10		T175	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T6	1		T10	1		T11	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T38	4		T133	7		T189	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T34	1		T45	7		T147	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T10	2		T138	3		T43	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1246	1			T14	12		T36	1		T15	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T132	1		T139	1		T176	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T17	1		T45	10		T39	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T37	11		T131	8		T137	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T80	1		T191	12		T188	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T34	15		T179	1		T144	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T14	5		T133	9		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T258	8		T167	11		T247	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T16	1		T81	9		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T10	2		T11	3		T38	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T45	12		T133	11		T256	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T12	7		T13	2		T46	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T198	19		T190	1		T218	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T14	2		T16	1		T130	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T34	11		T186	1		T131	23
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T339	1		T204	8		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T137	11		T296	1		T294	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14561	1			T1	20		T3	20		T4	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T6	3		T80	1		T215	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T133	2		T189	5		T207	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T45	7		T147	11		T244	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T43	1		T155	5		T241	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1251	1			T14	11		T154	18		T216	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T215	12		T257	4		T182	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T17	8		T45	7		T147	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T131	12		T137	11		T192	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T188	10		T245	12		T200	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T34	13		T144	3		T247	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T14	4		T143	7		T167	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T167	14		T247	3		T27	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T141	11		T168	10		T182	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T11	1		T134	2		T148	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T45	13		T133	10		T217	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T12	18		T13	1		T46	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T198	16		T190	8		T218	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T130	5		T134	8		T190	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T131	18		T207	4		T259	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T339	7		T204	7		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T137	12		T296	14		T294	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T32	1		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T6	1		T215	12		T201	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T25	2		T218	1		T203	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T131	23		T44	1		T142	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T314	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T215	9		T187	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T38	4		T138	7		T133	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T6	3		T34	1		T80	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T10	2		T138	3		T43	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T14	12		T167	13		T149	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T176	5		T215	14		T136	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T36	1		T17	1		T39	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T37	11		T132	1		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T45	10		T188	1		T148	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T34	15		T179	1		T144	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T80	1		T191	12		T240	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T258	8		T167	11		T247	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T14	5		T81	9		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T10	2		T191	11		T148	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T16	1		T45	12		T133	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T11	3		T12	7		T13	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T190	1		T256	14		T313	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T14	2		T16	1		T130	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1479	1			T15	2		T18	19		T34	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14502	1			T1	20		T3	20		T4	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T25	1		T218	3		T203	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T131	18		T210	17		T307	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T314	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T215	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T133	2		T207	11		T192	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T6	1		T45	7		T147	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T43	1		T189	5		T155	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T14	11		T167	24		T259	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T215	12		T257	4		T182	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T17	8		T147	9		T140	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T131	12		T137	11		T192	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T45	7		T188	10		T148	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T34	13		T144	3		T247	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T219	7		T266	3		T342	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T167	14		T247	3		T181	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T14	4		T141	11		T143	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T148	5		T203	8		T220	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T45	13		T133	10		T217	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T11	1		T12	18		T13	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T190	8		T242	3		T262	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T130	5		T134	8		T190	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1437	1			T154	18		T216	16		T146	16

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19070

1

T1

20

T3

20

T4

11

auto[1]

auto[0]

4212

1

T6

1

T11

1

T12

18