Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23282

1

T1

20

T3

20

T4

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20063

1

T1

20

T3

20

T4

11

auto[ADC_CTRL_FILTER_COND_OUT]

3219

1

T6

4

T11

4

T13

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17818

1

T1

20

T3

20

T4

11

auto[1]

5464

1

T11

4

T12

25

T13

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19546

1

T1

20

T3

20

T4

11

auto[1]

3736

1

T6

2

T10

2

T11

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	191	1			T36	1		T138	7		T131	20
values[0]	92	1			T137	21		T218	12		T239	3
values[1]	484	1			T11	4		T38	2		T34	11
values[2]	470	1			T10	2		T37	11		T44	1
values[3]	810	1			T10	2		T34	1		T45	39
values[4]	805	1			T13	3		T14	9		T38	4
values[5]	3125	1			T12	25		T14	2		T15	2
values[6]	594	1			T17	9		T130	6		T140	14
values[7]	750	1			T6	4		T14	23		T147	12
values[8]	637	1			T16	1		T34	28		T198	35
values[9]	822	1			T16	1		T81	9		T46	17
minimum	14502	1			T1	20		T3	20		T4	11

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	543	1			T11	4		T38	2		T34	11
values[1]	496	1			T10	2		T37	11		T133	21
values[2]	950	1			T10	2		T13	3		T38	4
values[3]	2860	1			T12	25		T14	9		T15	2
values[4]	902	1			T14	2		T17	9		T45	17
values[5]	676	1			T14	23		T130	6		T147	12
values[6]	745	1			T6	4		T16	1		T34	28
values[7]	592	1			T131	41		T25	3		T142	1
values[8]	695	1			T36	1		T16	1		T81	9
values[9]	141	1			T131	20		T224	1		T287	32
minimum	14682	1			T1	20		T3	20		T4	11

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19070

1

T1

20

T3

20

T4

11

auto[1]

4212

1

T6

1

T11

1

T12

18

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T38	1		T34	1		T138	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T11	3		T132	1		T130	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T10	1		T37	1		T133	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T44	1		T215	13		T225	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T10	2		T45	14		T139	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T13	2		T38	2		T34	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1578	1			T12	19		T15	2		T18	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T14	5		T80	1		T191	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T17	9		T190	11		T137	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T14	1		T45	8		T186	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T14	12		T130	6		T140	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T147	12		T136	1		T179	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T34	14		T198	17		T189	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T6	3		T16	1		T140	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T142	1		T207	5		T226	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T131	19		T25	2		T167	25
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T36	1		T16	1		T81	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T176	1		T190	9		T148	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T131	13		T221	17		T234	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T224	1		T287	18		T236	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14447	1			T1	20		T3	20		T4	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T177	1		T152	1		T156	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T38	1		T34	10		T138	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T11	1		T138	14		T202	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T10	1		T37	10		T133	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T215	8		T332	9		T229	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T45	11		T191	11		T176	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T13	1		T38	2		T45	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	937	1			T12	6		T18	17		T175	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T14	4		T191	10		T192	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T137	10		T181	17		T231	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T14	1		T45	9		T176	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T14	11		T192	11		T168	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T136	7		T200	2		T178	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T34	14		T198	18		T189	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T6	1		T167	10		T181	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T207	13		T197	3		T214	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T131	22		T25	1		T167	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T81	8		T46	9		T138	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T176	5		T148	9		T233	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T131	7		T234	15		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T287	14		T236	1		T343	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T6	1		T10	1		T11	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T152	9		T239	10		T237	6

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T36	1		T138	1		T131	13
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T176	1		T259	10		T283	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T137	12		T218	12		T239	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T237	10		T238	12		T246	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T38	1		T34	1		T138	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T11	3		T132	1		T130	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T10	1		T37	1		T134	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T44	1		T141	12		T225	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T10	2		T45	14		T139	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T34	1		T45	8		T215	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T140	13		T135	1		T223	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T13	2		T14	5		T38	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1624	1			T12	19		T15	2		T18	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T14	1		T80	1		T45	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T17	9		T130	6		T140	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T179	1		T180	1		T150	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T14	12		T189	6		T143	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T6	3		T147	12		T140	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T34	14		T198	17		T51	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T16	1		T190	9		T56	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T16	1		T81	1		T46	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T131	19		T148	6		T25	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14397	1			T1	20		T3	20		T4	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T138	6		T131	7		T144	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T176	5		T259	3		T283	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T137	9		T239	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T237	6		T238	11		T246	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T38	1		T34	10		T138	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T11	1		T138	14		T202	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T10	1		T37	10		T134	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T141	10		T239	10		T158	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T45	11		T133	10		T191	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T45	6		T215	8		T167	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T223	3		T240	16		T197	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T13	1		T14	4		T38	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	980	1			T12	6		T18	17		T175	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T14	1		T45	9		T176	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T192	11		T232	11		T152	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T152	7		T210	2		T320	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T14	11		T189	4		T203	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T6	1		T136	7		T167	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T34	14		T198	18		T51	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T167	12		T99	6		T169	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T81	8		T46	9		T133	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T131	22		T148	9		T25	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T6	1		T10	1		T11	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T38	2		T34	11		T138	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T11	3		T132	1		T130	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T10	2		T37	11		T133	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T44	1		T215	9		T225	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T10	2		T45	12		T139	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T13	2		T38	4		T34	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1259	1			T12	7		T15	2		T18	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T14	5		T80	1		T191	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T17	1		T190	1		T137	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T14	2		T45	10		T186	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T14	12		T130	1		T140	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T147	1		T136	8		T179	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T34	15		T198	19		T189	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T6	3		T16	1		T140	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T142	1		T207	14		T226	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T131	23		T25	2		T167	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T36	1		T16	1		T81	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T176	6		T190	1		T148	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T131	8		T221	1		T234	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T224	1		T287	15		T236	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14546	1			T1	20		T3	20		T4	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T177	1		T152	10		T156	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T43	1		T207	11		T217	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T11	1		T130	5		T151	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T133	10		T134	8		T148	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T215	12		T243	25		T229	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T45	13		T188	10		T244	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T13	1		T45	7		T141	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1256	1			T12	18		T154	18		T216	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T14	4		T192	2		T208	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T17	8		T190	10		T137	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T45	7		T147	9		T245	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T14	11		T130	5		T140	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T147	11		T218	3		T200	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T34	13		T198	16		T189	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T6	1		T167	14		T219	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T207	4		T197	1		T214	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T131	18		T25	1		T167	24
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T46	7		T134	2		T201	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T190	8		T148	5		T155	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T131	12		T221	16		T234	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T287	17		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T133	2		T137	11		T218	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T237	9		T238	11		T279	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T36	1		T138	7		T131	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T176	6		T259	4		T283	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T137	10		T218	1		T239	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T237	7		T238	12		T246	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T38	2		T34	11		T138	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T11	3		T132	1		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T10	2		T37	11		T134	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T44	1		T141	11		T225	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T10	2		T45	12		T139	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T34	1		T45	7		T215	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T140	1		T135	1		T223	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T13	2		T14	5		T38	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1310	1			T12	7		T15	2		T18	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T14	2		T80	1		T45	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T17	1		T130	1		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T179	1		T180	1		T150	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T14	12		T189	5		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T6	3		T147	1		T140	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T34	15		T198	19		T51	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T16	1		T190	1		T56	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T16	1		T81	9		T46	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T131	23		T148	10		T25	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14502	1			T1	20		T3	20		T4	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T131	12		T144	3		T319	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T259	9		T315	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T137	11		T218	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T237	9		T238	11		T246	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T133	2		T43	1		T207	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T11	1		T130	5		T151	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T134	8		T148	9		T217	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T141	11		T344	9		T243	25
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T45	13		T133	10		T188	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T45	7		T215	12		T167	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T140	12		T223	10		T247	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T13	1		T14	4		T208	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1294	1			T12	18		T154	18		T216	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T45	7		T147	9		T192	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T17	8		T130	5		T140	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T210	4		T295	13		T322	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T14	11		T189	5		T143	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T6	1		T147	11		T167	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T34	13		T198	16		T207	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T190	8		T167	24		T219	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T46	7		T134	2		T201	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T131	18		T148	5		T25	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19070

1

T1

20

T3

20

T4

11

auto[1]

auto[0]

4212

1

T6

1

T11

1

T12

18