Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T224	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T137	12		T218	12		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T138	1		T237	10		T238	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T10	1		T38	1		T34	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T11	3		T132	1		T130	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T37	1		T44	1		T134	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T141	12		T217	3		T151	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T10	2		T45	14		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T34	1		T45	8		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T39	1		T140	13		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T13	2		T14	5		T38	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1674	1			T12	19		T15	2		T18	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T14	1		T80	1		T45	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T17	9		T147	10		T187	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T140	14		T137	13		T192	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T14	12		T130	6		T147	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T6	3		T140	1		T136	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T34	14		T198	17		T51	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T16	1		T190	9		T25	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T36	1		T16	1		T81	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T131	32		T176	1		T208	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14397	1			T1	20		T3	20		T4	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T137	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T138	14		T237	6		T238	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T10	1		T38	1		T34	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T11	1		T202	14		T203	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T37	10		T134	10		T148	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T141	10		T151	13		T239	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T45	11		T133	10		T191	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T45	6		T215	8		T167	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T223	3		T240	16		T197	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T13	1		T14	4		T38	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	968	1			T12	6		T18	17		T175	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T14	1		T45	9		T176	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T181	17		T232	11		T152	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T137	10		T192	11		T152	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T14	11		T189	4		T241	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T6	1		T136	7		T167	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T34	14		T198	18		T51	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T25	1		T167	12		T99	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T81	8		T46	9		T138	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T131	29		T176	5		T144	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T6	1		T10	1		T11	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T38	2		T34	11		T138	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T11	3		T132	1		T130	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T10	4		T37	11		T133	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T215	9		T51	1		T225	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T45	12		T39	1		T139	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T13	2		T14	5		T38	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1241	1			T12	7		T15	2		T18	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T80	1		T191	11		T192	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T17	1		T147	1		T190	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T14	2		T45	10		T186	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T14	12		T130	1		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T140	1		T136	8		T192	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T34	15		T198	19		T189	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T6	3		T140	1		T56	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T142	1		T207	14		T226	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T16	1		T131	23		T25	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T36	1		T16	1		T81	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T176	6		T190	1		T208	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T227	7		T228	1		T221	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T131	8		T155	10		T153	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14502	1			T1	20		T3	20		T4	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T133	2		T43	1		T207	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T11	1		T130	5		T217	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T133	10		T134	8		T148	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T215	12		T242	3		T243	25
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T45	13		T188	10		T244	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T13	1		T14	4		T45	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1272	1			T12	18		T154	18		T216	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T192	2		T208	5		T168	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T17	8		T147	9		T190	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T45	7		T137	12		T245	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T14	11		T130	5		T147	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T140	13		T192	9		T218	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T34	13		T198	16		T189	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T6	1		T143	7		T219	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T207	4		T197	1		T214	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T131	18		T25	1		T167	38
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T46	7		T134	2		T148	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T190	8		T208	6		T144	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T228	4		T221	16		T234	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T131	12		T155	11		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T224	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T137	10		T218	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T138	15		T237	7		T238	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T10	2		T38	2		T34	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T11	3		T132	1		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T37	11		T44	1		T134	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T141	11		T217	1		T151	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T10	2		T45	12		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T34	1		T45	7		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T39	1		T140	1		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T13	2		T14	5		T38	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1301	1			T12	7		T15	2		T18	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T14	2		T80	1		T45	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T17	1		T147	1		T187	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T140	1		T137	11		T192	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T14	12		T130	1		T147	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T6	3		T140	1		T136	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T34	15		T198	19		T51	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T16	1		T190	1		T25	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T36	1		T16	1		T81	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T131	31		T176	6		T208	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14502	1			T1	20		T3	20		T4	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T137	11		T218	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T237	9		T238	11		T246	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T133	2		T43	1		T207	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T11	1		T130	5		T203	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T134	8		T148	9		T27	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T141	11		T217	2		T151	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T45	13		T133	10		T188	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T45	7		T215	12		T167	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T140	12		T223	10		T247	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T13	1		T14	4		T208	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1341	1			T12	18		T154	18		T216	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T45	7		T192	2		T245	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T17	8		T147	9		T181	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T140	13		T137	12		T192	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T14	11		T130	5		T147	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T6	1		T143	7		T167	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T34	13		T198	16		T207	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T190	8		T25	1		T167	24
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T46	7		T134	2		T148	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T131	30		T208	6		T144	3

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19070

1

T1

20

T3

20

T4

11

auto[1]

auto[0]

4212

1

T6

1

T11

1

T12

18