Summary for Variable clk_gate_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for clk_gate_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 23282 1 T1 20 T3 20 T4 11


Summary for Variable cond_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cond_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[ADC_CTRL_FILTER_COND_IN] 20026 1 T1 20 T3 20 T4 11
auto[ADC_CTRL_FILTER_COND_OUT] 3256 1 T11 4 T12 25 T13 3


Summary for Variable en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for en_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 17794 1 T1 20 T3 20 T4 11
auto[1] 5488 1 T14 11 T36 1 T15 2


Summary for Variable interrupt_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for interrupt_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 19546 1 T1 20 T3 20 T4 11
auto[1] 3736 1 T6 2 T10 2 T11 2


Summary for Variable max_v_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 12 0 12 100.00


User Defined Bins for max_v_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
maximum 3 1 T44 1 T248 1 T157 1
values[0] 8 1 T38 2 T249 3 T250 3
values[1] 594 1 T6 4 T13 3 T45 14
values[2] 860 1 T12 25 T81 9 T45 25
values[3] 538 1 T16 1 T17 9 T37 11
values[4] 636 1 T14 32 T36 1 T38 4
values[5] 2798 1 T10 2 T11 4 T15 2
values[6] 773 1 T138 15 T131 20 T25 3
values[7] 816 1 T10 2 T14 2 T80 1
values[8] 581 1 T34 39 T46 17 T186 1
values[9] 1173 1 T16 1 T80 1 T45 17
minimum 14502 1 T1 20 T3 20 T4 11


Summary for Variable min_v_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 12 1 11 91.67


User Defined Bins for min_v_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
maximum 0 1 1


Covered bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
values[0] 754 1 T6 4 T13 3 T38 2
values[1] 760 1 T12 25 T16 1 T37 11
values[2] 724 1 T14 32 T130 6 T133 30
values[3] 2732 1 T36 1 T15 2 T17 9
values[4] 651 1 T10 2 T132 1 T138 15
values[5] 791 1 T10 2 T11 4 T14 2
values[6] 766 1 T80 1 T138 3 T43 5
values[7] 602 1 T34 39 T46 17 T186 1
values[8] 810 1 T16 1 T80 1 T133 9
values[9] 166 1 T45 17 T233 13 T232 3
minimum 14526 1 T1 20 T3 20 T4 11


Summary for Variable wakeup_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wakeup_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 19070 1 T1 20 T3 20 T4 11
auto[1] 4212 1 T6 1 T11 1 T12 18


Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 6 42 87.50 6


Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes
interrupt_cp   min_v_cp   cond_cp   COUNT   AT LEAST   NUMBER   STATUS   
* [maximum] * -- -- 4
* [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] -- -- 2


Covered bins
interrupt_cp   min_v_cp   cond_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 223 1 T6 3 T38 1 T45 14
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 218 1 T13 2 T45 8 T138 1
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 264 1 T37 1 T34 1 T81 1
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 209 1 T12 19 T16 1 T130 6
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 142 1 T14 17 T133 11 T51 1
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 219 1 T130 6 T133 3 T176 1
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 1524 1 T15 2 T18 2 T166 2
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 186 1 T36 1 T17 9 T38 2
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 197 1 T10 2 T132 1 T189 6
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 158 1 T138 1 T131 19 T215 13
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 279 1 T10 1 T14 1 T190 9
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 179 1 T11 3 T131 13 T147 12
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 214 1 T80 1 T43 4 T134 3
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 258 1 T138 1 T137 13 T143 8
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 133 1 T34 1 T139 1 T140 14
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 245 1 T34 14 T46 8 T186 1
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 178 1 T16 1 T133 1 T191 1
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 240 1 T80 1 T137 12 T192 10
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 60 1 T45 8 T232 1 T248 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 20 1 T233 1 T251 1 T252 15
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 14400 1 T1 20 T3 20 T4 11
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_IN] 158 1 T6 1 T38 1 T45 11
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 155 1 T13 1 T45 6 T138 6
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 169 1 T37 10 T81 8 T191 10
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 118 1 T12 6 T148 9 T197 3
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 163 1 T14 15 T133 10 T51 6
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 200 1 T133 6 T176 4 T181 29
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 939 1 T18 17 T175 8 T253 9
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 83 1 T38 2 T176 5 T189 1
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 118 1 T189 4 T207 11 T203 2
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 178 1 T138 14 T131 22 T215 8
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 255 1 T10 1 T14 1 T25 1
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 78 1 T11 1 T131 7 T254 2
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 164 1 T43 1 T134 2 T167 10
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 130 1 T138 2 T137 10 T168 14
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 63 1 T34 10 T134 10 T178 2
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 161 1 T34 14 T46 9 T167 18
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 201 1 T133 8 T191 11 T176 3
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 191 1 T137 9 T192 11 T155 9
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 56 1 T45 9 T232 2 T183 2
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 30 1 T233 12 T252 10 T255 8
auto[1] minimum auto[ADC_CTRL_FILTER_COND_IN] 126 1 T6 1 T10 1 T11 1


Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 4 44 91.67 4


Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes
interrupt_cpmax_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [maximum] * -- -- 2


Uncovered bins
interrupt_cp   max_v_cp   cond_cp   COUNT   AT LEAST   NUMBER   STATUS   
[auto[0]] [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] 0 1 1
[auto[1]] [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] 0 1 1


Covered bins
interrupt_cp   max_v_cp   cond_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] maximum auto[ADC_CTRL_FILTER_COND_IN] 2 1 T44 1 T248 1 - -
auto[0] maximum auto[ADC_CTRL_FILTER_COND_OUT] 1 1 T157 1 - - - -
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 1 1 T38 1 - - - -
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 5 1 T249 3 T250 2 - -
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 203 1 T6 3 T39 1 T140 13
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 160 1 T13 2 T45 8 T138 1
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 248 1 T81 1 T45 14 T198 17
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 261 1 T12 19 T130 6 T148 6
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 108 1 T37 1 T34 1 T133 11
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 160 1 T16 1 T17 9 T130 6
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 171 1 T14 17 T135 1 T256 1
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 171 1 T36 1 T38 2 T139 1
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 1510 1 T10 2 T15 2 T18 2
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 234 1 T11 3 T131 19 T176 1
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 281 1 T25 2 T215 13 T207 12
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 178 1 T138 1 T131 13 T215 13
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 290 1 T10 1 T14 1 T80 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 176 1 T138 1 T147 12 T257 5
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 100 1 T34 1 T139 1 T43 4
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 236 1 T34 14 T46 8 T186 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 303 1 T16 1 T45 8 T133 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 350 1 T80 1 T137 12 T192 10
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 14397 1 T1 20 T3 20 T4 11
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_IN] 1 1 T38 1 - - - -
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 1 1 T250 1 - - - -
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 145 1 T6 1 T201 1 T199 2
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 86 1 T13 1 T45 6 T138 6
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 168 1 T81 8 T45 11 T198 18
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 183 1 T12 6 T148 9 T202 14
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 127 1 T37 10 T133 10 T258 7
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 143 1 T133 6 T176 4 T181 29
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 173 1 T14 15 T256 13 T144 6
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 121 1 T38 2 T189 1 T136 7
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 877 1 T18 17 T175 8 T253 9
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 177 1 T11 1 T131 22 T176 5
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 215 1 T25 1 T215 13 T207 11
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 99 1 T138 14 T131 7 T215 8
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 247 1 T10 1 T14 1 T134 12
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 103 1 T138 2 T257 10 T168 14
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 92 1 T34 10 T43 1 T259 3
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 153 1 T34 14 T46 9 T167 18
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 262 1 T45 9 T133 8 T191 11
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 258 1 T137 9 T192 11 T233 12
auto[1] minimum auto[ADC_CTRL_FILTER_COND_IN] 105 1 T6 1 T10 1 T11 1


Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 7 41 85.42 7


Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes
wakeup_cp   min_v_cp   cond_cp   COUNT   AT LEAST   NUMBER   STATUS   
[auto[0]] [maximum] * -- -- 2
[auto[1]] [maximum] * -- -- 2
[auto[1]] [minimum] * -- -- 2


Uncovered bins
wakeup_cpmin_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] 0 1 1


Covered bins
wakeup_cp   min_v_cp   cond_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 203 1 T6 3 T38 2 T45 12
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 196 1 T13 2 T45 7 T138 7
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 211 1 T37 11 T34 1 T81 9
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 156 1 T12 7 T16 1 T130 1
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 194 1 T14 17 T133 11 T51 7
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 232 1 T130 1 T133 7 T176 5
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 1256 1 T15 2 T18 19 T166 2
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 120 1 T36 1 T17 1 T38 4
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 154 1 T10 2 T132 1 T189 5
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 208 1 T138 15 T131 23 T215 9
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 295 1 T10 2 T14 2 T190 1
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 103 1 T11 3 T131 8 T147 1
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 201 1 T80 1 T43 4 T134 3
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 167 1 T138 3 T137 11 T143 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 83 1 T34 11 T139 1 T140 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 188 1 T34 15 T46 10 T186 1
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 238 1 T16 1 T133 9 T191 12
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 234 1 T80 1 T137 10 T192 12
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 71 1 T45 10 T232 3 T248 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 34 1 T233 13 T251 1 T252 11
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 14526 1 T1 20 T3 20 T4 11
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_IN] 178 1 T6 1 T45 13 T198 16
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 177 1 T13 1 T45 7 T190 10
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 222 1 T188 10 T148 9 T27 1
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 171 1 T12 18 T130 5 T148 5
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 111 1 T14 15 T133 10 T196 5
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 187 1 T130 5 T133 2 T181 22
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 1207 1 T154 18 T216 16 T146 16
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 149 1 T17 8 T219 13 T260 11
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 161 1 T189 5 T207 11 T208 6
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 128 1 T131 18 T215 12 T197 10
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 239 1 T190 8 T25 1 T215 12
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 154 1 T11 1 T131 12 T147 11
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 177 1 T43 1 T134 2 T167 14
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 221 1 T137 12 T143 7 T168 10
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 113 1 T140 13 T134 8 T217 2
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 218 1 T34 13 T46 7 T167 12
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 141 1 T244 4 T220 16 T213 2
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 197 1 T137 11 T192 9 T155 11
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 45 1 T45 7 T183 2 T261 6
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 16 1 T252 14 T255 2 - -


Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 6 42 87.50 6


Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes
wakeup_cp   max_v_cp   cond_cp   COUNT   AT LEAST   NUMBER   STATUS   
[auto[1]] [maximum] * -- -- 2
[auto[1]] [minimum] * -- -- 2


Uncovered bins
wakeup_cp   max_v_cp   cond_cp   COUNT   AT LEAST   NUMBER   STATUS   
[auto[0]] [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] 0 1 1
[auto[1]] [values[0]] [auto[ADC_CTRL_FILTER_COND_IN]] 0 1 1


Covered bins
wakeup_cp   max_v_cp   cond_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] maximum auto[ADC_CTRL_FILTER_COND_IN] 2 1 T44 1 T248 1 - -
auto[0] maximum auto[ADC_CTRL_FILTER_COND_OUT] 1 1 T157 1 - - - -
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 2 1 T38 2 - - - -
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 4 1 T249 2 T250 2 - -
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 188 1 T6 3 T39 1 T140 1
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 117 1 T13 2 T45 7 T138 7
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 205 1 T81 9 T45 12 T198 19
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 221 1 T12 7 T130 1 T148 10
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 155 1 T37 11 T34 1 T133 11
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 173 1 T16 1 T17 1 T130 1
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 207 1 T14 17 T135 1 T256 14
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 154 1 T36 1 T38 4 T139 1
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 1194 1 T10 2 T15 2 T18 19
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 221 1 T11 3 T131 23 T176 6
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 255 1 T25 2 T215 14 T207 12
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 121 1 T138 15 T131 8 T215 9
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 290 1 T10 2 T14 2 T80 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 131 1 T138 3 T147 1 T257 11
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 114 1 T34 11 T139 1 T43 4
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 182 1 T34 15 T46 10 T186 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 318 1 T16 1 T45 10 T133 9
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 313 1 T80 1 T137 10 T192 12
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 14502 1 T1 20 T3 20 T4 11
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 2 1 T249 1 T250 1 - -
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 160 1 T6 1 T140 12 T201 1
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 129 1 T13 1 T45 7 T190 10
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 211 1 T45 13 T198 16 T188 10
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 223 1 T12 18 T130 5 T148 5
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 80 1 T133 10 T148 9 T196 5
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 130 1 T17 8 T130 5 T133 2
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 137 1 T14 15 T208 5 T144 3
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 138 1 T219 13 T260 24 T262 12
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 1193 1 T154 18 T216 16 T146 16
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 190 1 T11 1 T131 18 T197 10
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 241 1 T25 1 T215 12 T207 11
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 156 1 T131 12 T215 12 T137 12
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 247 1 T134 10 T141 11 T207 4
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 148 1 T147 11 T257 4 T168 10
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 78 1 T43 1 T140 13 T259 9
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 207 1 T34 13 T46 7 T143 7
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 247 1 T45 7 T244 4 T217 2
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 295 1 T137 11 T192 9 T218 16


Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 2 2 50.00 2


Automatically Generated Cross Bins for wakeup_gated_xp

Element holes
wakeup_cpclk_gate_cpCOUNTAT LEASTNUMBERSTATUS
* [auto[1]] -- -- 2


Covered bins
wakeup_cp   clk_gate_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] auto[0] 19070 1 T1 20 T3 20 T4 11
auto[1] auto[0] 4212 1 T6 1 T11 1 T12 18