Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23282

1

T1

20

T3

20

T4

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19770

1

T1

20

T3

20

T4

11

auto[ADC_CTRL_FILTER_COND_OUT]

3512

1

T10

2

T11

4

T12

25

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17390

1

T1

20

T3

20

T4

11

auto[1]

5892

1

T10

2

T11

4

T12

25

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19546

1

T1

20

T3

20

T4

11

auto[1]

3736

1

T6

2

T10

2

T11

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	18	1			T140	1		T263	12		T264	5
values[0]	18	1			T208	6		T245	10		T261	2
values[1]	834	1			T10	2		T34	11		T81	9
values[2]	3071	1			T13	3		T15	2		T18	19
values[3]	754	1			T140	27		T188	11		T190	11
values[4]	506	1			T12	25		T37	11		T38	2
values[5]	644	1			T16	2		T80	1		T39	1
values[6]	558	1			T14	9		T45	25		T147	22
values[7]	552	1			T6	4		T11	4		T14	23
values[8]	524	1			T10	2		T14	2		T36	1
values[9]	1301	1			T34	28		T45	17		T138	7
minimum	14502	1			T1	20		T3	20		T4	11

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1003	1			T10	2		T34	11		T81	9
values[1]	3069	1			T13	3		T15	2		T18	19
values[2]	675	1			T12	25		T37	11		T38	2
values[3]	624	1			T16	1		T34	1		T139	1
values[4]	571	1			T16	1		T80	1		T39	1
values[5]	602	1			T14	32		T45	25		T147	10
values[6]	480	1			T6	4		T11	4		T46	17
values[7]	592	1			T10	2		T14	2		T36	1
values[8]	946	1			T34	28		T45	31		T139	1
values[9]	178	1			T138	7		T144	10		T223	14
minimum	14542	1			T1	20		T3	20		T4	11

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19070

1

T1

20

T3

20

T4

11

auto[1]

4212

1

T6

1

T11

1

T12

18

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T25	2		T189	6		T192	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T10	1		T34	1		T81	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1619	1			T13	2		T15	2		T18	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T190	11		T215	13		T51	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T140	14		T141	12		T240	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T12	19		T37	1		T38	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T139	1		T133	11		T225	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T16	1		T34	1		T131	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T16	1		T80	1		T39	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T198	17		T202	1		T155	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T45	14		T134	3		T244	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T14	17		T147	10		T258	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T6	3		T130	6		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T11	3		T46	8		T207	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T10	2		T14	1		T17	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T36	1		T38	2		T191	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T34	14		T203	5		T265	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	332	1			T45	16		T139	1		T131	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T138	1		T144	4		T266	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T223	11		T218	12		T150	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14411	1			T1	20		T3	20		T4	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T191	1		T267	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T25	1		T189	4		T192	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T10	1		T34	10		T81	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	949	1			T13	1		T18	17		T175	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T215	13		T51	6		T207	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T141	10		T155	9		T268	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T12	6		T37	10		T38	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T133	10		T199	2		T211	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T131	22		T133	8		T176	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T148	9		T196	12		T197	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T198	18		T202	14		T155	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T45	11		T134	2		T244	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T14	15		T258	7		T137	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T6	1		T138	14		T189	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T11	1		T46	9		T207	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T14	1		T176	4		T136	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T38	2		T191	10		T176	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T34	14		T203	2		T265	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T45	15		T131	7		T134	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T138	6		T144	6		T32	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T223	3		T182	3		T269	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T6	1		T10	1		T11	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T191	11		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T263	1		T264	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T140	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T208	6		T245	4		T261	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T25	2		T189	6		T208	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T10	1		T34	1		T81	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1645	1			T13	2		T15	2		T18	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T215	13		T51	1		T201	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T140	14		T141	12		T240	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T140	13		T188	11		T190	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T139	1		T133	11		T225	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T12	19		T37	1		T38	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T16	1		T80	1		T39	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T16	1		T131	19		T198	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T45	14		T147	12		T134	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T14	5		T147	10		T258	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T6	3		T132	1		T138	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T11	3		T14	12		T46	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T10	2		T14	1		T17	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T36	1		T38	2		T45	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	317	1			T34	14		T138	1		T144	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	465	1			T45	8		T139	1		T131	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14397	1			T1	20		T3	20		T4	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T263	11		T264	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T245	6		T261	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T25	1		T189	4		T203	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T10	1		T34	10		T81	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	993	1			T13	1		T18	17		T175	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T215	8		T51	6		T201	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T141	10		T155	9		T268	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T207	11		T256	13		T181	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T133	10		T211	9		T99	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T12	6		T37	10		T38	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T199	2		T197	12		T152	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T131	22		T198	18		T176	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T45	11		T134	2		T148	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T14	4		T258	7		T137	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T6	1		T138	14		T189	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T11	1		T14	11		T46	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T14	1		T176	4		T136	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T38	2		T45	6		T191	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T34	14		T138	6		T144	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T45	9		T131	7		T134	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T6	1		T10	1		T11	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T25	2		T189	5		T192	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T10	2		T34	11		T81	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1280	1			T13	2		T15	2		T18	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T190	1		T215	14		T51	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T140	1		T141	11		T240	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T12	7		T37	11		T38	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T139	1		T133	11		T225	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T16	1		T34	1		T131	23
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T16	1		T80	1		T39	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T198	19		T202	15		T155	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T45	12		T134	3		T244	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T14	17		T147	1		T258	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T6	3		T130	1		T138	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T11	3		T46	10		T207	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T10	2		T14	2		T17	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T36	1		T38	4		T191	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T34	15		T203	3		T265	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T45	17		T139	1		T131	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T138	7		T144	7		T266	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T223	4		T218	1		T150	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14516	1			T1	20		T3	20		T4	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T191	12		T267	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T25	1		T189	5		T192	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T130	5		T133	2		T215	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1288	1			T13	1		T154	18		T216	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T190	10		T215	12		T207	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T140	13		T141	11		T155	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T12	18		T140	12		T188	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T133	10		T99	15		T103	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T131	18		T148	9		T167	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T147	11		T190	8		T148	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T198	16		T155	5		T262	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T45	13		T134	2		T244	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T14	15		T147	9		T137	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T6	1		T130	5		T167	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T11	1		T46	7		T207	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T17	8		T181	9		T266	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T220	16		T178	7		T270	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T34	13		T203	4		T206	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T45	14		T131	12		T134	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T144	3		T266	3		T271	21
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T223	10		T218	11		T182	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T272	13		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T263	12		T264	5		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T140	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T208	1		T245	7		T261	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T25	2		T189	5		T208	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T10	2		T34	11		T81	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1328	1			T13	2		T15	2		T18	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T215	9		T51	7		T201	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T140	1		T141	11		T240	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T140	1		T188	1		T190	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T139	1		T133	11		T225	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T12	7		T37	11		T38	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T16	1		T80	1		T39	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T16	1		T131	23		T198	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T45	12		T147	1		T134	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T14	5		T147	1		T258	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T6	3		T132	1		T138	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T11	3		T14	12		T46	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T10	2		T14	2		T17	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T36	1		T38	4		T45	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T34	15		T138	7		T144	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	328	1			T45	10		T139	1		T131	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14502	1			T1	20		T3	20		T4	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T208	5		T245	3		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T25	1		T189	5		T208	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T130	5		T133	2		T215	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1310	1			T13	1		T154	18		T216	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T215	12		T201	1		T137	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T140	13		T141	11		T155	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T140	12		T188	10		T190	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T133	10		T247	3		T99	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T12	18		T148	9		T167	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T143	7		T168	7		T197	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T131	18		T198	16		T155	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T45	13		T147	11		T134	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T14	4		T147	9		T137	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T6	1		T167	12		T217	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T11	1		T14	11		T46	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T17	8		T130	5		T203	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T45	7		T93	14		T178	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T34	13		T144	3		T266	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	407	1			T45	7		T131	12		T134	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19070

1

T1

20

T3

20

T4

11

auto[1]

auto[0]

4212

1

T6

1

T11

1

T12

18