Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23282

1

T1

20

T3

20

T4

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20037

1

T1

20

T3

20

T4

11

auto[ADC_CTRL_FILTER_COND_OUT]

3245

1

T6

4

T10

2

T14

9

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17403

1

T1

20

T3

20

T4

11

auto[1]

5879

1

T6

4

T13

3

T14

23

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19546

1

T1

20

T3

20

T4

11

auto[1]

3736

1

T6

2

T10

2

T11

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	6	1			T273	6		-	-		-	-
values[0]	77	1			T45	14		T151	31		T183	6
values[1]	766	1			T14	23		T16	1		T45	25
values[2]	791	1			T186	1		T138	15		T131	20
values[3]	655	1			T37	11		T34	29		T39	1
values[4]	585	1			T16	1		T81	9		T132	1
values[5]	475	1			T12	25		T38	2		T191	11
values[6]	687	1			T80	1		T138	7		T139	1
values[7]	417	1			T17	9		T45	17		T147	22
values[8]	3159	1			T15	2		T18	19		T38	4
values[9]	1162	1			T6	4		T10	4		T11	4
minimum	14502	1			T1	20		T3	20		T4	11

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	968	1			T14	23		T45	14		T130	6
values[1]	718	1			T16	1		T45	25		T186	1
values[2]	669	1			T37	11		T34	29		T132	1
values[3]	598	1			T38	2		T81	9		T133	9
values[4]	462	1			T12	25		T16	1		T80	1
values[5]	707	1			T45	17		T138	7		T139	1
values[6]	2940	1			T15	2		T17	9		T18	19
values[7]	575	1			T13	3		T38	4		T198	35
values[8]	820	1			T6	4		T10	4		T11	4
values[9]	272	1			T46	17		T143	8		T219	8
minimum	14553	1			T1	20		T3	20		T4	11

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19070

1

T1

20

T3

20

T4

11

auto[1]

4212

1

T6

1

T11

1

T12

18

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T14	12		T130	6		T138	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	340	1			T45	8		T133	11		T43	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T45	14		T186	1		T148	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T16	1		T131	13		T25	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T37	1		T34	15		T138	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T132	1		T39	1		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T38	1		T81	1		T133	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T141	12		T274	1		T65	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T12	19		T16	1		T176	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T80	1		T191	1		T140	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T138	1		T51	1		T207	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T45	8		T139	1		T133	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1630	1			T15	2		T17	9		T18	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T191	1		T140	14		T215	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T13	2		T198	17		T258	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T38	2		T176	1		T215	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T10	2		T11	3		T14	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T6	3		T10	1		T14	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T46	8		T275	1		T276	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T143	8		T219	8		T260	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14428	1			T1	20		T3	20		T4	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T136	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T14	11		T138	14		T199	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T45	6		T133	10		T43	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T45	11		T148	9		T137	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T131	7		T25	1		T85	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T37	10		T34	14		T138	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T220	12		T214	14		T268	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T38	1		T81	8		T133	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T141	10		T277	8		T210	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T12	6		T176	9		T259	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T191	10		T167	18		T158	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T138	6		T51	6		T207	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T45	9		T133	8		T155	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	980	1			T18	17		T175	8		T131	22
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T191	11		T215	8		T262	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T13	1		T198	18		T258	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T38	2		T176	3		T215	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T11	1		T14	1		T207	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T6	1		T10	1		T14	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T46	9		T276	3		T169	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T278	13		T103	11		T279	21
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T6	1		T10	1		T11	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T136	7		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T273	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T183	4		T280	1		T281	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T45	8		T151	18		T169	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T14	12		T45	14		T130	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T16	1		T133	11		T43	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T186	1		T138	1		T148	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T131	13		T25	2		T211	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T37	1		T34	15		T138	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T39	1		T140	1		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T16	1		T81	1		T133	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T132	1		T139	1		T141	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T12	19		T38	1		T134	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T191	1		T44	1		T167	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T138	1		T176	2		T51	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T80	1		T139	1		T133	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T17	9		T147	12		T192	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T45	8		T147	10		T191	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1649	1			T15	2		T18	2		T166	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T38	2		T140	14		T176	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	347	1			T10	2		T11	3		T13	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T6	3		T10	1		T14	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14397	1			T1	20		T3	20		T4	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T273	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T183	2		T281	16		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T45	6		T151	13		T169	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T14	11		T45	11		T245	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T133	10		T43	1		T148	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T138	14		T148	9		T199	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T131	7		T25	1		T211	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T37	10		T34	14		T138	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T210	16		T282	11		T85	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T81	8		T133	6		T201	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T141	10		T214	14		T277	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T12	6		T38	1		T134	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T191	10		T167	18		T239	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T138	6		T176	9		T51	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T133	8		T155	5		T28	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T192	11		T210	2		T99	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T45	9		T191	11		T182	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1001	1			T18	17		T175	8		T131	22
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T38	2		T176	3		T215	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T11	1		T13	1		T14	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T6	1		T10	1		T14	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T6	1		T10	1		T11	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T14	12		T130	1		T138	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T45	7		T133	11		T43	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T45	12		T186	1		T148	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T16	1		T131	8		T25	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T37	11		T34	16		T138	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T132	1		T39	1		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T38	2		T81	9		T133	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T141	11		T274	1		T65	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T12	7		T16	1		T176	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T80	1		T191	11		T140	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T138	7		T51	7		T207	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T45	10		T139	1		T133	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1302	1			T15	2		T17	1		T18	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T191	12		T140	1		T215	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T13	2		T198	19		T258	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T38	4		T176	4		T215	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T10	2		T11	3		T14	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T6	3		T10	2		T14	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T46	10		T275	1		T276	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T143	1		T219	1		T260	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14516	1			T1	20		T3	20		T4	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T136	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T14	11		T130	5		T245	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T45	7		T133	10		T43	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T45	13		T148	9		T137	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T131	12		T25	1		T161	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T34	13		T190	10		T189	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T220	12		T214	11		T268	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T133	2		T134	2		T192	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T141	11		T210	17		T213	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T12	18		T259	9		T257	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T140	12		T167	12		T247	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T207	11		T181	15		T168	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T45	7		T147	9		T155	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1308	1			T17	8		T130	5		T131	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T140	13		T215	12		T242	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T13	1		T198	16		T244	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T215	12		T223	10		T245	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T11	1		T207	4		T208	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T6	1		T14	4		T220	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T46	7		T276	12		T271	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T143	7		T219	7		T260	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T283	13		T284	16		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T273	6		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T183	4		T280	1		T281	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T45	7		T151	14		T169	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T14	12		T45	12		T130	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T16	1		T133	11		T43	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T186	1		T138	15		T148	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T131	8		T25	2		T211	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T37	11		T34	16		T138	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T39	1		T140	1		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T16	1		T81	9		T133	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T132	1		T139	1		T141	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T12	7		T38	2		T134	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T191	11		T44	1		T167	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T138	7		T176	11		T51	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T80	1		T139	1		T133	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T17	1		T147	1		T192	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T45	10		T147	1		T191	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1326	1			T15	2		T18	19		T166	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T38	4		T140	1		T176	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T10	2		T11	3		T13	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	332	1			T6	3		T10	2		T14	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14502	1			T1	20		T3	20		T4	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T183	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T45	7		T151	17		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T14	11		T45	13		T130	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T133	10		T43	1		T148	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T148	9		T247	3		T241	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T131	12		T25	1		T220	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T34	13		T189	5		T137	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T210	17		T282	11		T285	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T133	2		T190	10		T201	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T141	11		T214	11		T268	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T12	18		T134	2		T257	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T167	12		T286	2		T287	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T207	11		T259	9		T181	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T140	12		T155	5		T218	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T17	8		T147	11		T192	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T45	7		T147	9		T182	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1324	1			T130	5		T131	18		T154	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T140	13		T215	12		T223	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T11	1		T13	1		T46	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T6	1		T14	4		T215	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19070

1

T1

20

T3

20

T4

11

auto[1]

auto[0]

4212

1

T6

1

T11

1

T12

18