Summary for Variable clk_gate_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for clk_gate_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 23282 1 T1 20 T3 20 T4 11


Summary for Variable cond_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cond_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[ADC_CTRL_FILTER_COND_IN] 19762 1 T1 20 T3 20 T4 11
auto[ADC_CTRL_FILTER_COND_OUT] 3520 1 T6 4 T14 25 T36 1


Summary for Variable en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for en_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 17465 1 T1 20 T3 20 T4 11
auto[1] 5817 1 T12 25 T14 2 T36 1


Summary for Variable interrupt_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for interrupt_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 19546 1 T1 20 T3 20 T4 11
auto[1] 3736 1 T6 2 T10 2 T11 2


Summary for Variable max_v_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 12 0 12 100.00


User Defined Bins for max_v_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
maximum 230 1 T81 9 T208 13 T217 3
values[0] 4 1 T288 3 T289 1 - -
values[1] 748 1 T10 2 T37 11 T38 6
values[2] 554 1 T36 1 T80 1 T133 21
values[3] 773 1 T10 2 T16 1 T46 17
values[4] 2984 1 T14 23 T15 2 T18 19
values[5] 717 1 T45 14 T39 1 T176 5
values[6] 728 1 T13 3 T34 11 T131 41
values[7] 516 1 T6 4 T12 25 T16 1
values[8] 796 1 T11 4 T34 28 T130 6
values[9] 730 1 T14 11 T17 9 T34 1
minimum 14502 1 T1 20 T3 20 T4 11


Summary for Variable min_v_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 12 1 11 91.67


User Defined Bins for min_v_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
maximum 0 1 1


Covered bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
values[0] 703 1 T10 2 T37 11 T38 2
values[1] 677 1 T36 1 T80 1 T133 21
values[2] 685 1 T10 2 T16 1 T45 17
values[3] 3094 1 T14 23 T15 2 T18 19
values[4] 652 1 T13 3 T39 1 T176 5
values[5] 803 1 T12 25 T34 11 T138 3
values[6] 404 1 T6 4 T11 4 T16 1
values[7] 746 1 T34 28 T147 12 T190 11
values[8] 740 1 T14 11 T17 9 T34 1
values[9] 119 1 T56 2 T197 5 T212 18
minimum 14659 1 T1 20 T3 20 T4 11


Summary for Variable wakeup_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wakeup_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 19070 1 T1 20 T3 20 T4 11
auto[1] 4212 1 T6 1 T11 1 T12 18


Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 4 44 91.67 4


Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes
interrupt_cpmin_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
* [maximum] * -- -- 4


Covered bins
interrupt_cp   min_v_cp   cond_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 293 1 T10 2 T38 1 T190 9
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 121 1 T37 1 T186 1 T198 17
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 198 1 T80 1 T133 11 T188 11
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 191 1 T36 1 T191 1 T179 1
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 144 1 T10 1 T46 8 T130 6
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 234 1 T16 1 T45 8 T133 1
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 1657 1 T15 2 T18 2 T80 1
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 242 1 T14 12 T45 22 T133 3
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 185 1 T13 2 T39 1 T51 1
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 186 1 T176 1 T148 6 T256 1
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 178 1 T12 19 T34 1 T138 1
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 239 1 T43 4 T201 2 T233 1
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 94 1 T11 3 T16 1 T132 1
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 126 1 T6 3 T167 13 T219 14
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 133 1 T34 14 T147 12 T141 12
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 330 1 T190 11 T189 6 T274 1
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 203 1 T14 5 T34 1 T208 7
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 251 1 T14 1 T17 9 T81 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 49 1 T56 2 T197 2 T212 9
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 18 1 T85 3 T170 1 T290 14
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 14431 1 T1 20 T3 20 T4 11
auto[0] minimum auto[ADC_CTRL_FILTER_COND_OUT] 43 1 T38 2 T138 1 T192 3
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_IN] 152 1 T38 1 T137 9 T192 11
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 137 1 T37 10 T198 18 T258 7
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 126 1 T133 10 T181 12 T220 12
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 162 1 T191 10 T240 16 T232 9
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 113 1 T10 1 T46 9 T138 14
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 194 1 T45 9 T133 8 T191 11
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 993 1 T18 17 T175 8 T131 7
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 202 1 T14 11 T45 17 T133 6
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 123 1 T13 1 T51 6 T207 24
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 158 1 T176 4 T148 9 T256 13
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 140 1 T12 6 T34 10 T138 2
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 246 1 T43 1 T201 1 T233 12
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 99 1 T11 1 T176 3 T144 6
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 85 1 T6 1 T167 18 T277 8
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 120 1 T34 14 T141 10 T232 2
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 163 1 T189 4 T241 10 T259 14
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 147 1 T14 4 T223 3 T155 9
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 139 1 T14 1 T81 8 T176 5
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 46 1 T197 3 T212 9 T239 10
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 6 1 T85 2 T290 4 - -
auto[1] minimum auto[ADC_CTRL_FILTER_COND_IN] 138 1 T6 1 T10 1 T11 1
auto[1] minimum auto[ADC_CTRL_FILTER_COND_OUT] 47 1 T38 2 T138 6 T192 2


Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 4 44 91.67 4


Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes
interrupt_cp   max_v_cp   cond_cp   COUNT   AT LEAST   NUMBER   STATUS   
* [values[0]] [auto[ADC_CTRL_FILTER_COND_OUT]] -- -- 2
* [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] -- -- 2


Covered bins
interrupt_cp   max_v_cp   cond_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] maximum auto[ADC_CTRL_FILTER_COND_IN] 63 1 T208 7 T223 11 T197 2
auto[0] maximum auto[ADC_CTRL_FILTER_COND_OUT] 71 1 T81 1 T208 6 T217 3
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 2 1 T288 1 T289 1 - -
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 284 1 T10 2 T38 1 T134 9
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 132 1 T37 1 T38 2 T186 1
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 168 1 T80 1 T133 11 T181 14
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 159 1 T36 1 T191 1 T240 1
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 197 1 T10 1 T46 8 T138 1
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 244 1 T16 1 T133 1 T191 1
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 1632 1 T15 2 T18 2 T80 1
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 202 1 T14 12 T45 22 T133 3
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 192 1 T39 1 T25 2 T51 2
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 199 1 T45 8 T176 1 T215 13
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 158 1 T13 2 T34 1 T131 19
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 230 1 T43 4 T148 6 T201 2
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 104 1 T12 19 T16 1 T132 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 178 1 T6 3 T167 13 T245 13
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 166 1 T11 3 T34 14 T130 6
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 315 1 T190 11 T189 6 T219 14
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 202 1 T14 5 T34 1 T56 2
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 251 1 T14 1 T17 9 T147 10
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 14397 1 T1 20 T3 20 T4 11
auto[1] maximum auto[ADC_CTRL_FILTER_COND_IN] 51 1 T223 3 T197 3 T212 9
auto[1] maximum auto[ADC_CTRL_FILTER_COND_OUT] 45 1 T81 8 T257 10 T278 13
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_IN] 2 1 T288 2 - - - -
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 171 1 T38 1 T134 10 T137 9
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 161 1 T37 10 T38 2 T138 6
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 86 1 T133 10 T181 12 T182 13
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 141 1 T191 10 T240 16 T291 10
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 157 1 T10 1 T46 9 T138 14
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 175 1 T133 8 T191 11 T168 14
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 968 1 T18 17 T175 8 T131 7
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 182 1 T14 11 T45 20 T133 6
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 124 1 T25 1 T51 6 T207 11
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 202 1 T45 6 T176 4 T215 13
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 144 1 T13 1 T34 10 T131 22
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 196 1 T43 1 T148 9 T201 1
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 66 1 T12 6 T138 2 T176 3
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 168 1 T6 1 T167 18 T245 14
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 167 1 T11 1 T34 14 T141 10
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 148 1 T189 4 T241 10 T259 14
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 156 1 T14 4 T155 9 T203 9
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 121 1 T14 1 T176 5 T211 9
auto[1] minimum auto[ADC_CTRL_FILTER_COND_IN] 105 1 T6 1 T10 1 T11 1


Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 4 44 91.67 4


Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes
wakeup_cpmin_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
* [maximum] * -- -- 4


Covered bins
wakeup_cp   min_v_cp   cond_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 191 1 T10 2 T38 2 T190 1
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 164 1 T37 11 T186 1 T198 19
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 161 1 T80 1 T133 11 T188 1
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 191 1 T36 1 T191 11 T179 1
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 143 1 T10 2 T46 10 T130 1
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 231 1 T16 1 T45 10 T133 9
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 1333 1 T15 2 T18 19 T80 1
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 239 1 T14 12 T45 19 T133 7
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 157 1 T13 2 T39 1 T51 7
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 189 1 T176 5 T148 10 T256 14
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 169 1 T12 7 T34 11 T138 3
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 285 1 T43 4 T201 2 T233 13
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 132 1 T11 3 T16 1 T132 1
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 106 1 T6 3 T167 19 T219 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 146 1 T34 15 T147 1 T141 11
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 201 1 T190 1 T189 5 T274 1
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 181 1 T14 5 T34 1 T208 1
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 179 1 T14 2 T17 1 T81 9
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 55 1 T56 2 T197 4 T212 10
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 11 1 T85 5 T170 1 T290 5
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 14548 1 T1 20 T3 20 T4 11
auto[0] minimum auto[ADC_CTRL_FILTER_COND_OUT] 58 1 T38 4 T138 7 T192 3
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_IN] 254 1 T190 8 T137 11 T192 9
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 94 1 T198 16 T260 13 T213 2
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 163 1 T133 10 T188 10 T181 13
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 162 1 T197 10 T103 8 T292 8
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 114 1 T46 7 T130 5 T254 2
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 197 1 T45 7 T168 10 T28 1
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 1317 1 T131 12 T154 18 T216 16
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 205 1 T14 11 T45 20 T133 2
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 151 1 T13 1 T207 15 T143 7
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 155 1 T148 5 T155 5 T218 3
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 149 1 T12 18 T131 18 T134 2
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 200 1 T43 1 T201 1 T245 15
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 61 1 T11 1 T130 5 T144 3
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 105 1 T6 1 T167 12 T219 13
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 107 1 T34 13 T147 11 T141 11
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 292 1 T190 10 T189 5 T241 14
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 169 1 T14 4 T208 6 T223 10
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 211 1 T17 8 T147 9 T140 12
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 40 1 T197 1 T212 8 T293 8
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 13 1 T290 13 - - - -
auto[1] minimum auto[ADC_CTRL_FILTER_COND_IN] 21 1 T134 8 T27 1 T290 12
auto[1] minimum auto[ADC_CTRL_FILTER_COND_OUT] 32 1 T192 2 T237 9 T294 11


Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 6 42 87.50 6


Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes
wakeup_cp   max_v_cp   cond_cp   COUNT   AT LEAST   NUMBER   STATUS   
[auto[1]] [values[0]] * -- -- 2
[auto[1]] [minimum] * -- -- 2


Uncovered bins
wakeup_cp   max_v_cp   cond_cp   COUNT   AT LEAST   NUMBER   STATUS   
[auto[0]] [values[0]] [auto[ADC_CTRL_FILTER_COND_OUT]] 0 1 1
[auto[0]] [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] 0 1 1


Covered bins
wakeup_cp   max_v_cp   cond_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] maximum auto[ADC_CTRL_FILTER_COND_IN] 62 1 T208 1 T223 4 T197 4
auto[0] maximum auto[ADC_CTRL_FILTER_COND_OUT] 60 1 T81 9 T208 1 T217 1
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 4 1 T288 3 T289 1 - -
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 215 1 T10 2 T38 2 T134 11
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 195 1 T37 11 T38 4 T186 1
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 116 1 T80 1 T133 11 T181 13
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 164 1 T36 1 T191 11 T240 17
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 194 1 T10 2 T46 10 T138 15
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 214 1 T16 1 T133 9 T191 12
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 1302 1 T15 2 T18 19 T80 1
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 212 1 T14 12 T45 22 T133 7
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 162 1 T39 1 T25 2 T51 8
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 238 1 T45 7 T176 5 T215 14
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 170 1 T13 2 T34 11 T131 23
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 235 1 T43 4 T148 10 T201 2
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 95 1 T12 7 T16 1 T132 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 195 1 T6 3 T167 19 T245 15
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 204 1 T11 3 T34 15 T130 1
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 181 1 T190 1 T189 5 T219 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 190 1 T14 5 T34 1 T56 2
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 160 1 T14 2 T17 1 T147 1
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 14502 1 T1 20 T3 20 T4 11
auto[1] maximum auto[ADC_CTRL_FILTER_COND_IN] 52 1 T208 6 T223 10 T197 1
auto[1] maximum auto[ADC_CTRL_FILTER_COND_OUT] 56 1 T208 5 T217 2 T257 4
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 240 1 T134 8 T190 8 T137 11
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 98 1 T198 16 T192 2 T213 2
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 138 1 T133 10 T181 13 T182 26
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 136 1 T260 13 T183 2 T295 13
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 160 1 T46 7 T188 10 T148 9
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 205 1 T168 10 T197 10 T28 1
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 1298 1 T130 5 T131 12 T154 18
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 172 1 T14 11 T45 20 T133 2
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 154 1 T25 1 T207 11 T143 7
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 163 1 T45 7 T215 12 T137 12
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 132 1 T13 1 T131 18 T134 2
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 191 1 T43 1 T148 5 T201 1
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 75 1 T12 18 T144 3 T218 16
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 151 1 T6 1 T167 12 T245 12
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 129 1 T11 1 T34 13 T130 5
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 282 1 T190 10 T189 5 T219 13
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 168 1 T14 4 T219 7 T155 11
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 212 1 T17 8 T147 9 T140 12


Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 2 2 50.00 2


Automatically Generated Cross Bins for wakeup_gated_xp

Element holes
wakeup_cpclk_gate_cpCOUNTAT LEASTNUMBERSTATUS
* [auto[1]] -- -- 2


Covered bins
wakeup_cp   clk_gate_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] auto[0] 19070 1 T1 20 T3 20 T4 11
auto[1] auto[0] 4212 1 T6 1 T11 1 T12 18