Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23282

1

T1

20

T3

20

T4

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19920

1

T1

20

T3

20

T4

11

auto[ADC_CTRL_FILTER_COND_OUT]

3362

1

T6

4

T10

2

T11

4

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17462

1

T1

20

T3

20

T4

11

auto[1]

5820

1

T6

4

T10

2

T11

4

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19546

1

T1

20

T3

20

T4

11

auto[1]

3736

1

T6

2

T10

2

T11

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	17	1			T39	1		T278	4		T169	1
values[0]	56	1			T182	27		T296	25		T297	1
values[1]	520	1			T13	3		T132	1		T139	1
values[2]	688	1			T6	4		T14	32		T17	9
values[3]	725	1			T14	2		T34	11		T45	14
values[4]	549	1			T16	1		T38	2		T45	42
values[5]	651	1			T10	2		T12	25		T37	11
values[6]	800	1			T80	1		T130	6		T199	3
values[7]	557	1			T36	1		T16	1		T38	4
values[8]	761	1			T11	4		T34	29		T138	7
values[9]	3456	1			T10	2		T15	2		T18	19
minimum	14502	1			T1	20		T3	20		T4	11

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	624	1			T13	3		T14	9		T132	1
values[1]	754	1			T6	4		T14	25		T17	9
values[2]	751	1			T16	1		T38	2		T34	11
values[3]	683	1			T45	17		T131	41		T133	9
values[4]	620	1			T10	2		T12	25		T37	11
values[5]	672	1			T36	1		T16	1		T80	1
values[6]	2852	1			T11	4		T15	2		T18	19
values[7]	767	1			T34	1		T138	7		T133	9
values[8]	844	1			T10	2		T81	9		T186	1
values[9]	177	1			T191	12		T192	5		T217	3
minimum	14538	1			T1	20		T3	20		T4	11

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19070

1

T1

20

T3

20

T4

11

auto[1]

4212

1

T6

1

T11

1

T12

18

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T13	2		T187	1		T274	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T14	5		T132	1		T140	27
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T14	1		T17	9		T80	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T6	3		T14	12		T140	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T38	1		T45	14		T258	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T16	1		T34	1		T43	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T45	8		T207	5		T240	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T131	19		T133	3		T147	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T10	1		T37	1		T56	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T12	19		T136	1		T151	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T36	1		T16	1		T130	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T80	1		T190	9		T199	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1562	1			T15	2		T18	2		T38	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T11	3		T138	1		T133	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T138	1		T148	6		T215	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T34	1		T133	1		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T39	1		T147	12		T176	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T10	2		T81	1		T186	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T226	1		T278	1		T99	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T191	1		T192	3		T217	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14397	1			T1	20		T3	20		T4	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T139	1		T265	1		T294	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T13	1		T262	19		T298	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T14	4		T134	10		T203	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T14	1		T45	6		T46	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T6	1		T14	11		T176	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T38	1		T45	11		T258	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T34	10		T43	1		T256	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T45	9		T207	13		T240	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T131	22		T133	6		T220	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T10	1		T37	10		T144	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T12	6		T136	7		T151	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T198	18		T223	3		T193	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T199	2		T155	9		T259	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	928	1			T18	17		T38	2		T34	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T11	1		T138	2		T133	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T138	6		T148	9		T215	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T133	8		T192	11		T167	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T176	5		T211	9		T203	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T81	8		T138	14		T191	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T278	13		T99	4		T299	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T191	11		T192	2		T155	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T6	1		T10	1		T11	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T265	11		T294	5		T300	14

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T39	1		T278	1		T301	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T169	1		T302	10		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T297	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T182	15		T296	25		T303	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T13	2		T187	1		T274	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T132	1		T139	1		T140	27
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T17	9		T80	1		T46	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T6	3		T14	17		T176	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T14	1		T45	8		T188	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T34	1		T43	4		T140	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T38	1		T45	22		T258	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T16	1		T133	3		T147	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T10	1		T37	1		T56	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T12	19		T131	19		T136	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T130	6		T144	4		T218	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T80	1		T199	1		T155	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T36	1		T16	1		T38	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T138	1		T133	11		T190	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T34	14		T138	1		T148	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T11	3		T34	1		T133	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1725	1			T15	2		T18	2		T166	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	388	1			T10	2		T81	1		T186	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14397	1			T1	20		T3	20		T4	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T278	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T182	12		T303	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T13	1		T262	19		T298	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T134	10		T241	10		T265	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T46	9		T131	7		T148	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T6	1		T14	15		T176	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T14	1		T45	6		T215	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T34	10		T43	1		T256	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T38	1		T45	20		T258	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T133	6		T304	15		T261	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T10	1		T37	10		T245	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T12	6		T131	22		T136	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T144	6		T197	12		T182	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T199	2		T155	9		T259	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T38	2		T198	18		T176	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T138	2		T133	10		T25	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T34	14		T138	6		T148	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T11	1		T133	8		T189	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1034	1			T18	17		T175	8		T176	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T81	8		T138	14		T191	21
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T6	1		T10	1		T11	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T13	2		T187	1		T274	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T14	5		T132	1		T140	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T14	2		T17	1		T80	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T6	3		T14	12		T140	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T38	2		T45	12		T258	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T16	1		T34	11		T43	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T45	10		T207	14		T240	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T131	23		T133	7		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T10	2		T37	11		T56	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T12	7		T136	8		T151	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T36	1		T16	1		T130	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T80	1		T190	1		T199	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1247	1			T15	2		T18	19		T38	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T11	3		T138	3		T133	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T138	7		T148	10		T215	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T34	1		T133	9		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T39	1		T147	1		T176	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T10	2		T81	9		T186	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T226	1		T278	14		T99	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T191	12		T192	3		T217	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14502	1			T1	20		T3	20		T4	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T139	1		T265	12		T294	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T13	1		T153	11		T262	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T14	4		T140	25		T134	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T17	8		T45	7		T46	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T6	1		T14	11		T143	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T45	13		T188	10		T215	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T43	1		T259	13		T260	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T45	7		T207	4		T245	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T131	18		T133	2		T147	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T144	3		T196	5		T276	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T12	18		T151	17		T213	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T130	5		T198	16		T223	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T190	8		T155	11		T259	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1243	1			T34	13		T130	5		T154	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T11	1		T133	10		T25	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T148	5		T215	12		T244	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T192	9		T167	12		T247	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T147	11		T219	20		T218	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T167	14		T208	6		T168	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T99	4		T305	6		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T192	2		T217	2		T155	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T294	2		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T39	1		T278	4		T301	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T169	1		T302	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T297	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T182	13		T296	2		T303	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T13	2		T187	1		T274	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T132	1		T139	1		T140	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T17	1		T80	1		T46	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T6	3		T14	17		T176	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T14	2		T45	7		T188	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T34	11		T43	4		T140	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T38	2		T45	22		T258	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T16	1		T133	7		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T10	2		T37	11		T56	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T12	7		T131	23		T136	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T130	1		T144	7		T218	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T80	1		T199	3		T155	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T36	1		T16	1		T38	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T138	3		T133	11		T190	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T34	15		T138	7		T148	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T11	3		T34	1		T133	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1388	1			T15	2		T18	19		T166	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	371	1			T10	2		T81	9		T186	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14502	1			T1	20		T3	20		T4	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T302	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T182	14		T296	23		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T13	1		T153	11		T262	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T140	25		T134	8		T241	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T17	8		T46	7		T131	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T6	1		T14	15		T143	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T45	7		T188	10		T215	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T43	1		T259	13		T220	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T45	20		T207	4		T247	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T133	2		T147	9		T304	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T245	12		T196	5		T93	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T12	18		T131	18		T151	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T130	5		T144	3		T218	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T155	11		T259	9		T276	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T130	5		T198	16		T134	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T133	10		T190	8		T25	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T34	13		T148	5		T244	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T11	1		T201	1		T192	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1371	1			T154	18		T216	16		T146	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T192	2		T167	14		T208	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19070

1

T1

20

T3

20

T4

11

auto[1]

auto[0]

4212

1

T6

1

T11

1

T12

18