Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23282

1

T1

20

T3

20

T4

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

17562

1

T1

20

T3

20

T4

11

auto[ADC_CTRL_FILTER_COND_OUT]

5720

1

T6

4

T14

32

T36

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17201

1

T1

20

T3

20

T4

11

auto[1]

6081

1

T11

4

T14

23

T15

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19546

1

T1

20

T3

20

T4

11

auto[1]

3736

1

T6

2

T10

2

T11

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	43	1			T210	34		T306	1		T307	8
values[0]	51	1			T34	1		T223	14		T187	1
values[1]	765	1			T6	4		T38	4		T80	1
values[2]	561	1			T10	2		T14	23		T138	3
values[3]	720	1			T36	1		T17	9		T39	1
values[4]	677	1			T37	11		T80	1		T132	1
values[5]	441	1			T34	28		T139	1		T191	12
values[6]	617	1			T14	9		T81	9		T133	9
values[7]	646	1			T10	2		T11	4		T13	3
values[8]	725	1			T38	2		T46	17		T130	6
values[9]	3534	1			T12	25		T14	2		T15	2
minimum	14502	1			T1	20		T3	20		T4	11

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1002	1			T6	4		T38	4		T34	1
values[1]	2709	1			T10	2		T36	1		T15	2
values[2]	637	1			T14	23		T17	9		T132	1
values[3]	713	1			T37	11		T80	1		T131	20
values[4]	557	1			T14	9		T34	28		T139	1
values[5]	503	1			T81	9		T258	8		T135	1
values[6]	754	1			T10	2		T11	4		T16	1
values[7]	719	1			T12	25		T13	3		T46	17
values[8]	1029	1			T14	2		T16	1		T34	11
values[9]	142	1			T130	6		T142	1		T137	23
minimum	14517	1			T1	20		T3	20		T4	11

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19070

1

T1

20

T3

20

T4

11

auto[1]

4212

1

T6

1

T11

1

T12

18

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	370	1			T38	2		T138	1		T133	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T6	3		T34	1		T80	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T10	2		T138	1		T43	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1582	1			T36	1		T15	2		T18	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T132	1		T139	1		T176	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T14	12		T17	9		T45	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T37	1		T131	13		T137	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T80	1		T191	1		T188	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T34	14		T144	4		T247	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T14	5		T139	1		T133	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T258	1		T167	15		T247	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T81	1		T135	1		T141	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T10	1		T11	3		T38	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T16	1		T45	14		T133	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T12	19		T13	2		T46	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T186	1		T198	17		T190	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T14	1		T16	1		T176	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	347	1			T34	1		T131	19		T44	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T130	6		T254	3		T213	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T142	1		T137	13		T231	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14397	1			T1	20		T3	20		T4	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T219	14		T308	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T38	2		T138	6		T133	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T6	1		T45	6		T215	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T138	2		T43	1		T176	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	946	1			T18	17		T175	8		T253	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T176	5		T215	13		T136	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T14	11		T45	9		T148	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T37	10		T131	7		T137	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T191	11		T245	14		T211	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T34	14		T144	6		T232	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T14	4		T133	8		T167	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T258	7		T167	10		T181	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T81	8		T141	10		T202	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T10	1		T11	1		T38	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T45	11		T133	10		T256	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T12	6		T13	1		T46	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T198	18		T262	19		T268	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T14	1		T176	3		T134	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T34	10		T131	22		T207	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T254	2		T213	2		T204	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T137	10		T231	8		T309	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T6	1		T10	1		T11	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T306	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T210	18		T307	8		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T223	11		T310	1		T311	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T34	1		T187	1		T312	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T38	2		T138	1		T133	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T6	3		T80	1		T45	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T10	2		T138	1		T43	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T14	12		T167	25		T149	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T176	1		T215	13		T136	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T36	1		T17	9		T39	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T37	1		T132	1		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T80	1		T45	8		T188	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T34	14		T144	4		T247	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T139	1		T191	1		T179	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T258	1		T167	15		T247	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T14	5		T81	1		T133	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T10	1		T11	3		T13	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T16	1		T45	14		T133	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T38	1		T46	8		T130	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T190	9		T256	1		T313	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T12	19		T14	1		T16	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1838	1			T15	2		T18	2		T34	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14397	1			T1	20		T3	20		T4	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T210	16		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T223	3		T310	14		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T38	2		T138	6		T133	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T6	1		T45	6		T215	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T138	2		T43	1		T189	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T14	11		T167	12		T259	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T176	4		T215	13		T136	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T245	20		T214	14		T213	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T37	10		T131	7		T176	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T45	9		T148	9		T211	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T34	14		T144	6		T232	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T191	11		T240	16		T202	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T258	7		T167	10		T181	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T14	4		T81	8		T133	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T10	1		T11	1		T13	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T45	11		T133	10		T220	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T38	1		T46	9		T134	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T256	13		T262	19		T268	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T12	6		T14	1		T138	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1172	1			T18	17		T34	10		T175	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T6	1		T10	1		T11	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	346	1			T38	4		T138	7		T133	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T6	3		T34	1		T80	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T10	2		T138	3		T43	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1258	1			T36	1		T15	2		T18	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T132	1		T139	1		T176	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T14	12		T17	1		T45	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T37	11		T131	8		T137	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T80	1		T191	12		T188	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T34	15		T144	7		T247	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T14	5		T139	1		T133	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T258	8		T167	11		T247	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T81	9		T135	1		T141	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T10	2		T11	3		T38	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T16	1		T45	12		T133	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T12	7		T13	2		T46	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T186	1		T198	19		T190	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T14	2		T16	1		T176	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T34	11		T131	23		T44	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T130	1		T254	3		T213	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T142	1		T137	11		T231	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14502	1			T1	20		T3	20		T4	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T219	1		T308	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T133	2		T189	5		T207	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T6	1		T45	7		T147	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T43	1		T155	5		T241	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1270	1			T154	18		T216	16		T146	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T215	12		T257	4		T182	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T14	11		T17	8		T45	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T131	12		T137	11		T192	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T188	10		T245	12		T200	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T34	13		T144	3		T247	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T14	4		T143	7		T167	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T167	14		T247	3		T181	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T141	11		T168	10		T196	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T11	1		T134	2		T148	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T45	13		T133	10		T217	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T12	18		T13	1		T46	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T198	16		T190	8		T218	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T134	8		T190	10		T25	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T131	18		T207	4		T259	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T130	5		T254	2		T213	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T137	12		T231	10		T296	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T219	13		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T306	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T210	17		T307	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T223	4		T310	15		T311	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T34	1		T187	1		T312	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T38	4		T138	7		T133	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T6	3		T80	1		T45	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T10	2		T138	3		T43	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T14	12		T167	13		T149	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T176	5		T215	14		T136	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T36	1		T17	1		T39	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T37	11		T132	1		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T80	1		T45	10		T188	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T34	15		T144	7		T247	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T139	1		T191	12		T179	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T258	8		T167	11		T247	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T14	5		T81	9		T133	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T10	2		T11	3		T13	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T16	1		T45	12		T133	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T38	2		T46	10		T130	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T190	1		T256	14		T313	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T12	7		T14	2		T16	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1528	1			T15	2		T18	19		T34	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14502	1			T1	20		T3	20		T4	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T210	17		T307	7		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T223	10		T314	5		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T315	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T133	2		T207	11		T192	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T6	1		T45	7		T147	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T43	1		T189	5		T155	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T14	11		T167	24		T259	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T215	12		T257	4		T182	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T17	8		T147	9		T140	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T131	12		T137	11		T192	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T45	7		T188	10		T148	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T34	13		T144	3		T247	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T219	7		T266	3		T197	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T167	14		T247	3		T181	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T14	4		T141	11		T143	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T11	1		T13	1		T148	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T45	13		T133	10		T217	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T46	7		T130	5		T140	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T190	8		T242	3		T262	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T12	18		T130	5		T134	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1482	1			T131	18		T154	18		T216	16

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

19070

1

T1

20

T3

20

T4

11

auto[1]

auto[0]

4212

1

T6

1

T11

1

T12

18