Summary for Variable clk_gate_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for clk_gate_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 23282 1 T1 20 T3 20 T4 11


Summary for Variable cond_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cond_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[ADC_CTRL_FILTER_COND_IN] 19986 1 T1 20 T3 20 T4 11
auto[ADC_CTRL_FILTER_COND_OUT] 3296 1 T6 4 T10 4 T14 9


Summary for Variable en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for en_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 17435 1 T1 20 T3 20 T4 11
auto[1] 5847 1 T6 4 T10 2 T13 3


Summary for Variable interrupt_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for interrupt_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 19546 1 T1 20 T3 20 T4 11
auto[1] 3736 1 T6 2 T10 2 T11 2


Summary for Variable max_v_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 12 0 12 100.00


User Defined Bins for max_v_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
maximum 238 1 T10 2 T14 2 T34 11
values[0] 46 1 T45 14 T133 21 T316 11
values[1] 792 1 T14 23 T16 1 T130 6
values[2] 765 1 T45 25 T186 1 T138 15
values[3] 652 1 T37 11 T34 29 T39 1
values[4] 588 1 T81 9 T132 1 T133 9
values[5] 562 1 T12 25 T16 1 T38 2
values[6] 615 1 T80 1 T138 7 T133 9
values[7] 503 1 T17 9 T45 17 T139 1
values[8] 3013 1 T15 2 T18 19 T38 4
values[9] 1006 1 T6 4 T10 2 T11 4
minimum 14502 1 T1 20 T3 20 T4 11


Summary for Variable min_v_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 12 1 11 91.67


User Defined Bins for min_v_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
maximum 0 1 1


Covered bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
values[0] 713 1 T14 23 T138 15 T43 5
values[1] 774 1 T16 1 T45 25 T186 1
values[2] 618 1 T37 11 T34 29 T132 1
values[3] 578 1 T16 1 T81 9 T133 9
values[4] 522 1 T12 25 T38 2 T80 1
values[5] 644 1 T45 17 T138 7 T139 1
values[6] 2917 1 T15 2 T17 9 T18 19
values[7] 569 1 T13 3 T38 4 T198 35
values[8] 942 1 T6 4 T10 4 T11 4
values[9] 192 1 T34 11 T144 10 T219 8
minimum 14813 1 T1 20 T3 20 T4 11


Summary for Variable wakeup_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wakeup_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 19070 1 T1 20 T3 20 T4 11
auto[1] 4212 1 T6 1 T11 1 T12 18


Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 4 44 91.67 4


Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes
interrupt_cpmin_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
* [maximum] * -- -- 4


Covered bins
interrupt_cp   min_v_cp   cond_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 236 1 T14 12 T138 1 T199 1
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 245 1 T43 4 T189 1 T137 13
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 239 1 T186 1 T148 10 T137 12
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 196 1 T16 1 T45 14 T131 13
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 152 1 T37 1 T34 15 T138 1
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 194 1 T132 1 T39 1 T139 1
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 143 1 T16 1 T81 1 T133 3
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 162 1 T141 12 T274 1 T197 2
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 183 1 T12 19 T38 1 T176 2
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 125 1 T80 1 T191 1 T140 13
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 166 1 T138 1 T51 1 T207 12
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 179 1 T45 8 T139 1 T133 1
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 1620 1 T15 2 T17 9 T18 2
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 183 1 T191 1 T140 14 T215 13
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 122 1 T13 2 T198 17 T135 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 202 1 T38 2 T176 1 T215 13
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 307 1 T11 3 T14 1 T46 8
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 225 1 T6 3 T10 3 T14 5
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 49 1 T144 4 T219 8 T278 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 61 1 T34 1 T260 12 T312 1
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 14467 1 T1 20 T3 20 T4 11
auto[0] minimum auto[ADC_CTRL_FILTER_COND_OUT] 90 1 T45 8 T133 11 T148 6
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_IN] 101 1 T14 11 T138 14 T199 2
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 131 1 T43 1 T189 1 T137 10
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 172 1 T148 9 T137 9 T202 14
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 167 1 T45 11 T131 7 T25 1
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 138 1 T37 10 T34 14 T138 2
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 134 1 T220 12 T214 14 T277 8
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 129 1 T81 8 T133 6 T134 2
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 144 1 T141 10 T197 3 T213 3
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 109 1 T12 6 T38 1 T176 9
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 105 1 T191 10 T167 18 T239 10
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 147 1 T138 6 T51 6 T207 11
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 152 1 T45 9 T133 8 T155 5
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 970 1 T18 17 T175 8 T131 22
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 144 1 T191 11 T215 8 T262 19
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 116 1 T13 1 T198 18 T244 7
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 129 1 T38 2 T176 3 T215 13
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 195 1 T11 1 T14 1 T46 9
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 215 1 T6 1 T10 1 T14 4
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 36 1 T144 6 T278 13 T169 2
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 46 1 T34 10 T317 10 T279 11
auto[1] minimum auto[ADC_CTRL_FILTER_COND_IN] 189 1 T6 1 T10 1 T11 1
auto[1] minimum auto[ADC_CTRL_FILTER_COND_OUT] 67 1 T45 6 T133 10 T148 9


Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 4 44 91.67 4


Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes
interrupt_cp   max_v_cp   cond_cp   COUNT   AT LEAST   NUMBER   STATUS   
* [values[0]] [auto[ADC_CTRL_FILTER_COND_IN]] -- -- 2
* [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] -- -- 2


Covered bins
interrupt_cp   max_v_cp   cond_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] maximum auto[ADC_CTRL_FILTER_COND_IN] 93 1 T14 1 T46 8 T207 5
auto[0] maximum auto[ADC_CTRL_FILTER_COND_OUT] 41 1 T10 1 T34 1 T155 13
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 30 1 T45 8 T133 11 T316 11
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 226 1 T14 12 T130 6 T245 4
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 272 1 T16 1 T43 4 T148 6
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 257 1 T186 1 T138 1 T148 10
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 178 1 T45 14 T131 13 T25 2
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 180 1 T37 1 T34 15 T138 1
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 198 1 T39 1 T139 1 T140 1
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 134 1 T81 1 T133 3 T190 11
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 158 1 T132 1 T141 12 T197 2
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 196 1 T12 19 T16 1 T38 1
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 136 1 T191 1 T140 13 T44 1
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 146 1 T138 1 T176 2 T51 1
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 170 1 T80 1 T133 1 T155 6
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 167 1 T17 9 T131 19 T147 12
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 136 1 T45 8 T139 1 T147 10
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 1606 1 T15 2 T18 2 T166 2
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 262 1 T38 2 T140 14 T176 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 282 1 T11 3 T13 2 T258 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 281 1 T6 3 T10 2 T14 5
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 14397 1 T1 20 T3 20 T4 11
auto[1] maximum auto[ADC_CTRL_FILTER_COND_IN] 52 1 T14 1 T46 9 T207 13
auto[1] maximum auto[ADC_CTRL_FILTER_COND_OUT] 52 1 T10 1 T34 10 T155 9
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 16 1 T45 6 T133 10 - -
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 162 1 T14 11 T245 6 T200 2
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 132 1 T43 1 T148 9 T189 1
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 147 1 T138 14 T148 9 T199 2
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 183 1 T45 11 T131 7 T25 1
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 163 1 T37 10 T34 14 T138 2
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 111 1 T220 12 T210 16 T282 11
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 133 1 T81 8 T133 6 T201 1
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 163 1 T141 10 T197 3 T214 14
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 107 1 T12 6 T38 1 T134 2
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 123 1 T191 10 T167 18 T239 10
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 152 1 T138 6 T176 9 T51 6
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 147 1 T133 8 T155 5 T182 12
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 100 1 T131 22 T192 11 T210 2
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 100 1 T45 9 T191 11 T317 8
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 976 1 T18 17 T175 8 T198 18
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 169 1 T38 2 T176 3 T215 8
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 205 1 T11 1 T13 1 T258 7
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 238 1 T6 1 T14 4 T215 13
auto[1] minimum auto[ADC_CTRL_FILTER_COND_IN] 105 1 T6 1 T10 1 T11 1


Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 4 44 91.67 4


Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes
wakeup_cpmin_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
* [maximum] * -- -- 4


Covered bins
wakeup_cp   min_v_cp   cond_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 134 1 T14 12 T138 15 T199 3
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 167 1 T43 4 T189 2 T137 11
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 209 1 T186 1 T148 10 T137 10
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 206 1 T16 1 T45 12 T131 8
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 168 1 T37 11 T34 16 T138 3
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 166 1 T132 1 T39 1 T139 1
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 160 1 T16 1 T81 9 T133 7
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 173 1 T141 11 T274 1 T197 4
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 136 1 T12 7 T38 2 T176 11
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 127 1 T80 1 T191 11 T140 1
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 175 1 T138 7 T51 7 T207 12
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 186 1 T45 10 T139 1 T133 9
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 1292 1 T15 2 T17 1 T18 19
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 172 1 T191 12 T140 1 T215 9
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 151 1 T13 2 T198 19 T135 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 165 1 T38 4 T176 4 T215 14
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 243 1 T11 3 T14 2 T46 10
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 260 1 T6 3 T10 4 T14 5
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 43 1 T144 7 T219 1 T278 14
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 55 1 T34 11 T260 1 T312 1
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 14599 1 T1 20 T3 20 T4 11
auto[0] minimum auto[ADC_CTRL_FILTER_COND_OUT] 83 1 T45 7 T133 11 T148 10
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_IN] 203 1 T14 11 T245 3 T247 3
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 209 1 T43 1 T137 12 T218 11
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 202 1 T148 9 T137 11 T241 14
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 157 1 T45 13 T131 12 T25 1
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 122 1 T34 13 T190 10 T189 5
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 162 1 T220 12 T214 11 T268 12
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 112 1 T133 2 T134 2 T192 2
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 133 1 T141 11 T197 1 T213 6
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 156 1 T12 18 T259 9 T257 4
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 103 1 T140 12 T167 12 T247 11
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 138 1 T207 11 T181 15 T168 10
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 145 1 T45 7 T147 9 T155 5
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 1298 1 T17 8 T130 5 T131 18
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 155 1 T140 13 T215 12 T242 3
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 87 1 T13 1 T198 16 T188 10
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 166 1 T215 12 T223 10 T245 12
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 259 1 T11 1 T46 7 T207 4
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 180 1 T6 1 T14 4 T143 7
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 42 1 T144 3 T219 7 T296 14
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 52 1 T260 11 T317 10 T228 4
auto[1] minimum auto[ADC_CTRL_FILTER_COND_IN] 57 1 T130 5 T213 2 T318 9
auto[1] minimum auto[ADC_CTRL_FILTER_COND_OUT] 74 1 T45 7 T133 10 T148 5


Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 5 43 89.58 5


Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes
wakeup_cpmax_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [minimum] * -- -- 2


Uncovered bins
wakeup_cp   max_v_cp   cond_cp   COUNT   AT LEAST   NUMBER   STATUS   
[auto[0]] [values[0]] [auto[ADC_CTRL_FILTER_COND_IN]] 0 1 1
[auto[0]] [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] 0 1 1
[auto[1]] [values[0]] [auto[ADC_CTRL_FILTER_COND_IN]] 0 1 1


Covered bins
wakeup_cp   max_v_cp   cond_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] maximum auto[ADC_CTRL_FILTER_COND_IN] 65 1 T14 2 T46 10 T207 14
auto[0] maximum auto[ADC_CTRL_FILTER_COND_OUT] 62 1 T10 2 T34 11 T155 11
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 19 1 T45 7 T133 11 T316 1
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 196 1 T14 12 T130 1 T245 7
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 174 1 T16 1 T43 4 T148 10
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 185 1 T186 1 T138 15 T148 10
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 220 1 T45 12 T131 8 T25 2
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 197 1 T37 11 T34 16 T138 3
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 144 1 T39 1 T139 1 T140 1
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 164 1 T81 9 T133 7 T190 1
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 191 1 T132 1 T141 11 T197 4
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 136 1 T12 7 T16 1 T38 2
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 148 1 T191 11 T140 1 T44 1
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 177 1 T138 7 T176 11 T51 7
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 180 1 T80 1 T133 9 T155 6
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 127 1 T17 1 T131 23 T147 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 122 1 T45 10 T139 1 T147 1
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 1303 1 T15 2 T18 19 T166 2
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 211 1 T38 4 T140 1 T176 4
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 258 1 T11 3 T13 2 T258 8
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 289 1 T6 3 T10 2 T14 5
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 14502 1 T1 20 T3 20 T4 11
auto[1] maximum auto[ADC_CTRL_FILTER_COND_IN] 80 1 T46 7 T207 4 T208 6
auto[1] maximum auto[ADC_CTRL_FILTER_COND_OUT] 31 1 T155 11 T260 11 T294 9
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 27 1 T45 7 T133 10 T316 10
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 192 1 T14 11 T130 5 T245 3
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 230 1 T43 1 T148 5 T137 12
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 219 1 T148 9 T247 3 T241 14
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 141 1 T45 13 T131 12 T25 1
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 146 1 T34 13 T189 5 T137 11
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 165 1 T220 12 T210 17 T282 11
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 103 1 T133 2 T190 10 T201 1
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 130 1 T141 11 T197 1 T214 11
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 167 1 T12 18 T134 2 T257 4
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 111 1 T140 12 T167 12 T296 16
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 121 1 T207 11 T259 9 T181 15
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 137 1 T155 5 T218 3 T247 11
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 140 1 T17 8 T131 18 T147 11
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 114 1 T45 7 T147 9 T260 13
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 1279 1 T130 5 T154 18 T216 16
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 220 1 T140 13 T215 12 T223 10
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 229 1 T11 1 T13 1 T244 4
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 230 1 T6 1 T14 4 T215 12


Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 2 2 50.00 2


Automatically Generated Cross Bins for wakeup_gated_xp

Element holes
wakeup_cpclk_gate_cpCOUNTAT LEASTNUMBERSTATUS
* [auto[1]] -- -- 2


Covered bins
wakeup_cp   clk_gate_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] auto[0] 19070 1 T1 20 T3 20 T4 11
auto[1] auto[0] 4212 1 T6 1 T11 1 T12 18