Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22968

1

T2

20

T3

20

T4

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19447

1

T2

20

T3

20

T4

1

auto[ADC_CTRL_FILTER_COND_OUT]

3521

1

T10

8

T15

8

T16

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16883

1

T2

20

T3

20

T4

1

auto[1]

6085

1

T10

3

T16

1

T18

5

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19141

1

T2

20

T3

20

T4

1

auto[1]

3827

1

T10

6

T11

1

T25

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	13	1			T234	13		-	-		-	-
values[0]	31	1			T168	1		T142	15		T235	10
values[1]	744	1			T10	5		T19	5		T186	6
values[2]	609	1			T43	11		T137	1		T81	1
values[3]	656	1			T10	3		T19	24		T42	7
values[4]	507	1			T11	2		T121	8		T80	14
values[5]	589	1			T13	4		T118	24		T138	10
values[6]	549	1			T16	1		T39	35		T173	3
values[7]	729	1			T15	8		T155	10		T168	1
values[8]	3186	1			T18	5		T20	28		T37	1
values[9]	1339	1			T14	2		T17	1		T120	18
minimum	14016	1			T2	20		T3	20		T4	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	865	1			T10	5		T19	5		T43	11
values[1]	711	1			T19	15		T121	12		T81	1
values[2]	656	1			T10	3		T11	2		T19	9
values[3]	467	1			T13	4		T121	8		T118	24
values[4]	554	1			T138	10		T236	27		T151	39
values[5]	671	1			T16	1		T173	3		T168	1
values[6]	3234	1			T15	8		T18	5		T20	28
values[7]	596	1			T120	17		T78	17		T80	11
values[8]	1043	1			T14	2		T17	1		T120	18
values[9]	155	1			T44	3		T138	15		T141	16
minimum	14016	1			T2	20		T3	20		T4	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18746

1

T2

20

T3

20

T4

1

auto[1]

4222

1

T10

1

T15

2

T19

26

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T19	5		T186	6		T137	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T10	3		T43	9		T168	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T237	1		T238	1		T239	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T19	15		T121	1		T81	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T11	1		T19	9		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T10	2		T42	6		T46	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T13	3		T121	1		T80	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T118	15		T138	1		T240	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T30	1		T170	1		T241	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T138	6		T236	15		T151	24
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T183	1		T122	1		T153	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T16	1		T173	1		T168	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1729	1			T18	1		T20	28		T37	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T15	6		T39	11		T82	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T120	9		T78	10		T242	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T80	11		T123	13		T197	22
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T14	1		T17	1		T120	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T45	8		T243	1		T244	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T138	7		T245	1		T232	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T44	2		T141	16		T169	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13898	1			T2	20		T3	20		T4	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T128	13		T246	1		T174	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T10	2		T43	2		T82	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T238	10		T239	1		T171	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T121	11		T82	15		T201	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T11	1		T247	1		T171	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T10	1		T42	1		T46	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T13	1		T121	7		T216	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T118	9		T138	1		T240	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T248	1		T249	11		T250	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T138	4		T236	12		T151	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T122	11		T153	10		T242	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T173	2		T251	12		T213	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1065	1			T18	4		T155	9		T165	21
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T15	2		T39	24		T82	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T120	8		T78	7		T242	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T123	8		T252	10		T253	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T14	1		T120	8		T151	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T45	3		T243	9		T244	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T138	8		T232	3		T250	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T44	1		T254	11		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T10	3		T25	2		T13	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T234	13		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T168	1		T142	15		T235	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T19	5		T186	6		T255	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T10	3		T80	8		T127	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T137	1		T237	1		T146	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T43	9		T81	1		T82	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T19	9		T137	1		T238	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T10	2		T19	15		T42	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T11	1		T121	1		T80	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T138	1		T256	1		T252	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T13	3		T30	1		T170	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T118	15		T138	6		T240	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T183	1		T122	1		T257	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T16	1		T39	11		T173	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T155	1		T197	10		T125	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T15	6		T168	1		T82	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1725	1			T18	1		T20	28		T37	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T80	11		T252	12		T258	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	342	1			T14	1		T17	1		T120	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	417	1			T44	2		T45	8		T243	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13898	1			T2	20		T3	20		T4	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T235	7		T259	4		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T174	11		T260	9		T214	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T10	2		T127	10		T174	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T128	13		T246	4		T261	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T43	2		T82	17		T123	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T238	10		T239	1		T171	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T10	1		T42	1		T46	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T11	1		T121	7		T247	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T138	1		T252	20		T262	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T13	1		T248	1		T249	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T118	9		T138	4		T240	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T122	11		T257	2		T246	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T39	24		T173	2		T251	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T155	9		T125	7		T153	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T15	2		T82	4		T124	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1058	1			T18	4		T120	8		T165	21
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T252	10		T55	3		T263	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T14	1		T120	8		T138	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T44	1		T45	3		T243	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T10	3		T25	2		T13	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T19	1		T186	1		T137	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T10	4		T43	8		T168	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T237	1		T238	11		T239	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T19	1		T121	12		T81	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T11	2		T19	1		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T10	3		T42	6		T46	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T13	4		T121	8		T80	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T118	10		T138	2		T240	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T30	1		T170	1		T241	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T138	5		T236	13		T151	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T183	1		T122	12		T153	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T16	1		T173	3		T168	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1416	1			T18	5		T20	3		T37	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T15	6		T39	25		T82	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T120	9		T78	8		T242	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T80	1		T123	9		T197	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T14	2		T17	1		T120	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T45	8		T243	10		T244	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T138	9		T245	1		T232	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T44	2		T141	1		T169	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14016	1			T2	20		T3	20		T4	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T19	4		T186	5		T146	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T10	1		T43	3		T80	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T146	14		T171	4		T264	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T19	14		T82	9		T201	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T19	8		T247	1		T171	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T42	1		T46	14		T140	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T80	13		T141	2		T265	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T118	14		T240	3		T169	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T207	11		T248	1		T249	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T138	5		T236	14		T151	22
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T153	10		T242	2		T126	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T140	4		T251	14		T156	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1378	1			T20	25		T164	15		T167	22
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T15	2		T39	10		T145	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T120	8		T78	9		T242	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T80	10		T123	12		T197	21
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T120	9		T129	12		T151	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T45	3		T142	13		T145	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T138	6		T232	11		T250	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T44	1		T141	15		T169	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T234	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T168	1		T142	1		T235	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T19	1		T186	1		T255	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T10	4		T80	1		T127	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T137	1		T237	1		T146	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T43	8		T81	1		T82	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T19	1		T137	1		T238	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T10	3		T19	1		T42	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T11	2		T121	8		T80	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T138	2		T256	1		T252	21
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T13	4		T30	1		T170	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T118	10		T138	5		T240	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T183	1		T122	12		T257	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T16	1		T39	25		T173	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T155	10		T197	1		T125	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T15	6		T168	1		T82	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1412	1			T18	5		T20	3		T37	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T80	1		T252	11		T258	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	327	1			T14	2		T17	1		T120	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	384	1			T44	2		T45	8		T243	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14016	1			T2	20		T3	20		T4	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T234	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T142	14		T235	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T19	4		T186	5		T146	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T10	1		T80	7		T127	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T146	14		T158	10		T266	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T43	3		T82	9		T123	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T19	8		T171	7		T267	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T19	14		T42	1		T46	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T80	13		T141	2		T247	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T252	18		T201	13		T159	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T248	1		T249	13		T250	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T118	14		T138	5		T240	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T207	19		T268	1		T269	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T39	10		T140	4		T251	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T197	9		T125	8		T153	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T15	2		T145	6		T127	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1371	1			T20	25		T120	8		T164	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T80	10		T252	11		T270	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T120	9		T129	12		T138	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	348	1			T44	1		T45	3		T141	15

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18746

1

T2

20

T3

20

T4

1

auto[1]

auto[0]

4222

1

T10

1

T15

2

T19

26

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22968

1

T2

20

T3

20

T4

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20031

1

T2

20

T3

20

T4

1

auto[ADC_CTRL_FILTER_COND_OUT]

2937

1

T11

2

T13

4

T15

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17119

1

T2

20

T3

20

T4

1

auto[1]

5849

1

T11

2

T15

8

T17

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19141

1

T2

20

T3

20

T4

1

auto[1]

3827

1

T10

6

T11

1

T25

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	5	1			T265	5		-	-		-	-
values[0]	27	1			T268	5		T271	10		T158	1
values[1]	589	1			T14	2		T16	1		T155	21
values[2]	799	1			T46	20		T43	11		T140	12
values[3]	863	1			T17	1		T39	35		T168	1
values[4]	501	1			T10	3		T42	7		T173	3
values[5]	3078	1			T11	2		T13	4		T18	5
values[6]	631	1			T120	18		T137	1		T82	5
values[7]	619	1			T15	8		T82	3		T139	13
values[8]	700	1			T120	17		T168	2		T129	13
values[9]	1140	1			T10	5		T19	20		T186	6
minimum	14016	1			T2	20		T3	20		T4	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	826	1			T16	1		T46	20		T43	11
values[1]	792	1			T14	2		T17	1		T140	12
values[2]	766	1			T39	35		T42	7		T173	3
values[3]	2997	1			T10	3		T18	5		T20	28
values[4]	622	1			T11	2		T13	4		T19	9
values[5]	660	1			T120	18		T137	1		T82	8
values[6]	603	1			T15	8		T129	13		T29	1
values[7]	657	1			T120	17		T168	2		T121	12
values[8]	831	1			T10	5		T19	20		T186	6
values[9]	197	1			T124	2		T272	1		T156	6
minimum	14017	1			T2	20		T3	20		T4	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18746

1

T2

20

T3

20

T4

1

auto[1]

4222

1

T10

1

T15

2

T19

26

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T46	15		T43	9		T155	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T16	1		T155	1		T138	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T14	1		T140	12		T82	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T17	1		T142	15		T152	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T42	6		T173	1		T168	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T39	11		T258	1		T128	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1712	1			T10	2		T18	1		T20	28
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T121	1		T132	1		T144	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T123	23		T144	1		T128	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T11	1		T13	3		T19	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T120	10		T137	1		T82	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T139	1		T236	15		T157	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T129	13		T240	4		T238	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T15	6		T29	1		T247	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T168	1		T121	1		T141	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T120	9		T168	1		T80	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T10	3		T19	5		T186	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T19	15		T121	1		T118	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T124	1		T272	1		T156	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T269	22		T273	3		T178	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13899	1			T2	20		T3	20		T4	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T46	5		T43	2		T155	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T155	9		T138	5		T122	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T14	1		T82	15		T124	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T152	6		T86	1		T176	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T42	1		T173	2		T243	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T39	24		T128	13		T266	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1018	1			T10	1		T18	4		T165	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T121	7		T171	5		T201	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T123	19		T232	3		T274	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T11	1		T13	1		T247	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T120	8		T82	6		T138	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T139	12		T236	12		T275	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T240	3		T238	11		T174	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T15	2		T247	1		T252	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T121	11		T125	12		T201	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T120	8		T143	15		T242	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T10	2		T45	3		T78	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T121	12		T118	9		T244	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T124	1		T276	14		T216	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T273	2		T277	8		T278	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T10	3		T25	2		T13	1