Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.67	99.07	96.67	100.00	100.00	98.82	98.33	90.82

Total tests in report: 919

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
56.91	56.91	88.22	88.22	50.31	50.31	83.77	83.77	32.43	32.43	73.62	73.62	64.61	64.61	5.42	5.42	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_poweron_counter.3936541682
78.31	21.40	98.23	10.01	84.60	34.29	96.92	13.15	64.86	32.43	97.33	23.71	87.48	22.87	18.72	13.30	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.885087558
82.39	4.08	98.26	0.03	84.93	0.33	96.92	0.00	91.89	27.03	97.39	0.06	87.48	0.00	19.84	1.12	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_fsm_reset.3973301159
85.20	2.81	98.76	0.50	92.67	7.74	96.92	0.00	91.89	0.00	98.20	0.81	90.15	2.67	27.78	7.94	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_wakeup.3508598688
86.48	1.29	98.88	0.12	93.08	0.41	96.92	0.00	91.89	0.00	98.39	0.19	90.15	0.00	36.06	8.29	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_clock_gating.3744731271
87.67	1.18	98.88	0.00	93.37	0.29	96.92	0.00	91.89	0.00	98.39	0.00	94.66	4.51	39.56	3.49	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.1062136776
88.62	0.95	98.88	0.00	93.58	0.21	97.39	0.47	94.59	2.70	98.45	0.06	95.16	0.50	42.28	2.72	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.3464404132
89.52	0.90	98.88	0.00	93.58	0.00	97.39	0.00	94.59	0.00	98.45	0.00	95.33	0.17	48.42	6.14	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_clock_gating.395929402
90.35	0.83	98.88	0.00	93.62	0.04	97.39	0.00	100.00	5.41	98.51	0.06	95.33	0.00	48.71	0.30	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_stress_all.3775799825
91.12	0.77	98.88	0.00	93.62	0.00	97.39	0.00	100.00	0.00	98.51	0.00	95.33	0.00	54.13	5.42	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_clock_gating.3415124227
91.77	0.64	98.88	0.00	93.62	0.00	97.39	0.00	100.00	0.00	98.51	0.00	95.83	0.50	58.12	3.99	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_both.4130055752
92.29	0.53	98.88	0.00	93.62	0.00	97.39	0.00	100.00	0.00	98.51	0.00	95.99	0.17	61.64	3.52	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_clock_gating.2619154613
92.77	0.48	98.88	0.00	94.40	0.78	97.39	0.00	100.00	0.00	98.63	0.12	95.99	0.00	64.09	2.45	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_both.735832152
93.21	0.43	98.92	0.03	94.52	0.12	99.76	2.37	100.00	0.00	98.70	0.06	96.33	0.33	64.21	0.12	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_sec_cm.4071213463
93.60	0.39	98.92	0.00	94.52	0.00	99.76	0.00	100.00	0.00	98.70	0.00	96.33	0.00	66.96	2.75	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_wakeup.2929206548
93.94	0.35	98.92	0.00	94.52	0.00	99.76	0.00	100.00	0.00	98.70	0.00	96.33	0.00	69.38	2.42	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_both.3061957647
94.21	0.26	98.92	0.00	94.52	0.00	99.76	0.00	100.00	0.00	98.70	0.00	96.66	0.33	70.88	1.50	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_wakeup.3914486751
94.46	0.26	98.92	0.00	94.57	0.04	99.76	0.00	100.00	0.00	98.70	0.00	96.66	0.00	72.62	1.75	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_interrupt_fixed.1504006943
94.69	0.23	98.92	0.00	95.68	1.11	99.76	0.00	100.00	0.00	98.70	0.00	96.83	0.17	72.95	0.32	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_errors.3388919676
94.91	0.22	98.92	0.00	95.68	0.00	99.76	0.00	100.00	0.00	98.70	0.00	96.83	0.00	74.52	1.57	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_clock_gating.2108992123
95.13	0.21	98.92	0.00	95.68	0.00	99.76	0.00	100.00	0.00	98.70	0.00	96.83	0.00	76.02	1.50	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_both.961805046
95.33	0.20	98.98	0.06	95.92	0.25	99.76	0.00	100.00	0.00	98.82	0.12	97.83	1.00	76.02	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3203538639
95.53	0.19	98.98	0.00	95.92	0.00	99.76	0.00	100.00	0.00	98.82	0.00	97.83	0.00	77.36	1.35	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_stress_all.1738781119
95.70	0.17	98.98	0.00	95.92	0.00	99.76	0.00	100.00	0.00	98.82	0.00	98.00	0.17	78.39	1.02	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_both.2406639276
95.85	0.15	98.98	0.00	95.92	0.00	99.76	0.00	100.00	0.00	98.82	0.00	98.00	0.00	79.44	1.05	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_clock_gating.4206969120
95.97	0.12	98.98	0.00	95.92	0.00	99.76	0.00	100.00	0.00	98.82	0.00	98.00	0.00	80.28	0.85	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_wakeup.2198683013
96.07	0.11	98.98	0.00	95.92	0.00	99.76	0.00	100.00	0.00	98.82	0.00	98.00	0.00	81.03	0.75	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_both.3024801488
96.17	0.10	98.98	0.00	95.92	0.00	99.76	0.00	100.00	0.00	98.82	0.00	98.00	0.00	81.73	0.70	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_wakeup.3492407244
96.27	0.10	98.98	0.00	95.92	0.00	99.76	0.00	100.00	0.00	98.82	0.00	98.00	0.00	82.43	0.70	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_clock_gating.2938491702
96.37	0.09	98.98	0.00	95.92	0.00	99.76	0.00	100.00	0.00	98.82	0.00	98.00	0.00	83.08	0.65	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_stress_all.630390171
96.44	0.08	98.98	0.00	95.92	0.00	99.76	0.00	100.00	0.00	98.82	0.00	98.00	0.00	83.63	0.55	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_both.2768623796
96.52	0.07	98.98	0.00	95.92	0.00	99.76	0.00	100.00	0.00	98.82	0.00	98.00	0.00	84.15	0.52	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_clock_gating.4155811958
96.59	0.07	98.98	0.00	95.92	0.00	99.76	0.00	100.00	0.00	98.82	0.00	98.00	0.00	84.68	0.52	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_stress_all.3893630547
96.66	0.07	98.98	0.00	95.92	0.00	99.76	0.00	100.00	0.00	98.82	0.00	98.00	0.00	85.15	0.47	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_stress_all.461043573
96.73	0.06	99.07	0.09	96.05	0.12	100.00	0.24	100.00	0.00	98.82	0.00	98.00	0.00	85.15	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_alert_test.1414870676
96.79	0.06	99.07	0.00	96.34	0.29	100.00	0.00	100.00	0.00	98.82	0.00	98.00	0.00	85.30	0.15	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.3898327982
96.85	0.06	99.07	0.00	96.54	0.21	100.00	0.00	100.00	0.00	98.82	0.00	98.00	0.00	85.50	0.20	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.3231516768
96.90	0.06	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.00	0.00	85.90	0.40	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_both.485643177
96.96	0.05	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.00	0.00	86.27	0.37	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_wakeup.3575627241
97.01	0.05	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.33	86.27	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_rw.910633003
97.05	0.05	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	86.60	0.32	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_both.1208665319
97.10	0.05	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	86.92	0.32	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_interrupt.2625453064
97.14	0.04	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	87.22	0.30	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_interrupt.831955481
97.18	0.04	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	87.50	0.27	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_clock_gating.2223259681
97.22	0.04	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	87.75	0.25	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_clock_gating.3659492662
97.24	0.03	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	87.95	0.20	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.1402846024
97.27	0.03	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	88.15	0.20	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_clock_gating.3168497787
97.30	0.03	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	88.35	0.20	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_interrupt.3463163424
97.32	0.02	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	88.50	0.15	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_wakeup_fixed.239715979
97.34	0.02	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	88.64	0.15	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_fsm_reset.1624533543
97.36	0.02	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	88.77	0.12	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_stress_all.81510072
97.38	0.02	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	88.89	0.12	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_stress_all.75213111
97.40	0.02	99.07	0.00	96.54	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	89.02	0.12	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_stress_all.3347016959
97.42	0.02	99.07	0.00	96.67	0.12	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	89.02	0.00	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_errors.1545914176
97.43	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	89.12	0.10	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_clock_gating.1059808136
97.44	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	89.22	0.10	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_wakeup.2469755389
97.46	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	89.32	0.10	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_wakeup.2758549054
97.47	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	89.42	0.10	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_fsm_reset.1893251074
97.49	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	89.52	0.10	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_wakeup.4183855378
97.50	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	89.62	0.10	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_clock_gating.2102952676
97.51	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	89.72	0.10	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_wakeup.1765943190
97.53	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	89.79	0.07	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_wakeup.2884593570
97.54	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	89.87	0.07	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_stress_all.1695227498
97.55	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	89.94	0.07	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_interrupt.982882874
97.56	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	90.02	0.07	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_stress_all.3719572983
97.57	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	90.09	0.07	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_interrupt.3872317660
97.58	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	90.17	0.07	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_wakeup.13409334
97.59	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	90.22	0.05	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.910148350
97.59	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	90.27	0.05	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_wakeup.980192073
97.60	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	90.32	0.05	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_interrupt.853456631
97.61	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	90.37	0.05	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_polled.1642917014
97.61	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	90.42	0.05	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_both.3881694559
97.62	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	90.47	0.05	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_fsm_reset.4262050820
97.63	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	90.52	0.05	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_clock_gating.3856512774
97.64	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	90.57	0.05	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_fsm_reset.1998780472
97.64	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	90.62	0.05	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_both.3109034167
97.65	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	90.64	0.02	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.3916827245
97.65	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	90.67	0.02	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_interrupt.229840786
97.65	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	90.69	0.02	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_both.2077045367
97.66	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	90.72	0.02	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_clock_gating.1664751244
97.66	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	90.74	0.02	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.1686703490
97.66	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	90.77	0.02	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_fsm_reset.496142863
97.67	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	90.79	0.02	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_clock_gating.4226439525
97.67	0.01	99.07	0.00	96.67	0.00	100.00	0.00	100.00	0.00	98.82	0.00	98.33	0.00	90.82	0.02	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.31089280

---

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.3075748144
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.2067758416
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.4112076670
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.2891121108
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_intr_test.1610527095
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.820680448
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.511190378
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.459162300
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.2428236609
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.907685585
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.3281244784
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_rw.3349181342
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_intr_test.1419015489
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.1520569675
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.507519198
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_rw.2392788239
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_intr_test.605840026
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.270764045
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_errors.3378630732
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.1938878238
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.2427602510
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_rw.200236763
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_intr_test.4110665115
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.2086186094
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_errors.979174123
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2621132148
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.1637240981
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_rw.100766687
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_intr_test.3073471318
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.1866544944
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_errors.1655492422
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.2501822743
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_rw.3251703664
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_intr_test.2904597046
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.3091834346
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_errors.2731481305
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.817713290
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.1336498803
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_rw.518334033
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_intr_test.1719458734
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.3910190373
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_errors.3425440222
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.700421071
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_rw.3753765087
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_intr_test.971139485
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.3031529260
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_errors.3624280481
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.3498934400
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2731396635
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_rw.2460401456
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_intr_test.829925127
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.837717064
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_errors.250249632
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.435358769
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.4043658391
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_rw.3642421622
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_intr_test.289158631
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.791187266
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_errors.1292662183
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.292638728
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.3864516737
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_csr_rw.926855891
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_intr_test.4274005644
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.1693879313
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_errors.90166946
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1172475620
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.322748450
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_csr_rw.4281278736
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_intr_test.1778934087
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.1932093540
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_tl_errors.1345919263
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.308361853
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.3828962806
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.3918046309
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.3935043699
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.2498672822
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1238070892
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_intr_test.2927795506
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.2946396862
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1744953135
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.1857153670
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/20.adc_ctrl_intr_test.3678412512
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/21.adc_ctrl_intr_test.2220349026
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/22.adc_ctrl_intr_test.1026391083
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/23.adc_ctrl_intr_test.2395704016
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/24.adc_ctrl_intr_test.3394626414
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/25.adc_ctrl_intr_test.4007334789
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/26.adc_ctrl_intr_test.2660429143
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/27.adc_ctrl_intr_test.607556009
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/28.adc_ctrl_intr_test.1871706075
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/29.adc_ctrl_intr_test.428216616
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.475306923
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.2649040880
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.749990072
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_rw.2082214796
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_intr_test.3168397311
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.117539755
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/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_poweron_counter.3341011676
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_smoke.2739773678
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.561861462

---

Total test records in report: 919

---

tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html

---

TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T1	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_alert_test.1414870676			Oct 14 10:26:12 PM UTC 24	Oct 14 10:26:15 PM UTC 24	472291079 ps
T2	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_smoke.1360723808			Oct 14 10:26:11 PM UTC 24	Oct 14 10:26:17 PM UTC 24	6022217244 ps
T3	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_smoke.3096368507			Oct 14 10:26:13 PM UTC 24	Oct 14 10:26:20 PM UTC 24	5635091653 ps
T4	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.1443508766			Oct 14 10:26:12 PM UTC 24	Oct 14 10:26:23 PM UTC 24	1133027449 ps
T5	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_poweron_counter.3936541682			Oct 14 10:26:15 PM UTC 24	Oct 14 10:26:24 PM UTC 24	2734934462 ps
T21	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_alert_test.3263425068			Oct 14 10:26:23 PM UTC 24	Oct 14 10:26:26 PM UTC 24	427615798 ps
T6	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_lowpower_counter.2305460874			Oct 14 10:26:12 PM UTC 24	Oct 14 10:26:28 PM UTC 24	24473007642 ps
T7	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_poweron_counter.4255305913			Oct 14 10:26:11 PM UTC 24	Oct 14 10:26:28 PM UTC 24	5306542915 ps
T8	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_lowpower_counter.3580348646			Oct 14 10:26:16 PM UTC 24	Oct 14 10:26:29 PM UTC 24	22583285504 ps
T9	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_smoke.702193318			Oct 14 10:26:25 PM UTC 24	Oct 14 10:26:32 PM UTC 24	5888957992 ps
T10	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.885087558			Oct 14 10:26:18 PM UTC 24	Oct 14 10:26:33 PM UTC 24	18317092920 ps
T22	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_sec_cm.4071213463			Oct 14 10:26:12 PM UTC 24	Oct 14 10:26:42 PM UTC 24	7309650911 ps
T11	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_clock_gating.1485717351			Oct 14 10:26:11 PM UTC 24	Oct 14 10:26:44 PM UTC 24	166594805200 ps
T12	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_poweron_counter.1799194912			Oct 14 10:26:41 PM UTC 24	Oct 14 10:26:46 PM UTC 24	4760610195 ps
T23	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_sec_cm.2559824431			Oct 14 10:26:21 PM UTC 24	Oct 14 10:26:49 PM UTC 24	8203263720 ps
T24	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_alert_test.1102166838			Oct 14 10:26:50 PM UTC 24	Oct 14 10:26:52 PM UTC 24	505636171 ps
T25	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_stress_all.2926640109			Oct 14 10:26:46 PM UTC 24	Oct 14 10:26:53 PM UTC 24	1254849016 ps
T26	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_smoke.371120903			Oct 14 10:26:54 PM UTC 24	Oct 14 10:26:57 PM UTC 24	5793105008 ps
T13	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.1477444030			Oct 14 10:26:46 PM UTC 24	Oct 14 10:26:59 PM UTC 24	8618961435 ps
T27	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_sec_cm.1231718106			Oct 14 10:26:50 PM UTC 24	Oct 14 10:27:10 PM UTC 24	4333668678 ps
T40	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_lowpower_counter.685062091			Oct 14 10:26:42 PM UTC 24	Oct 14 10:27:17 PM UTC 24	33176190539 ps
T41	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_poweron_counter.834345754			Oct 14 10:27:15 PM UTC 24	Oct 14 10:27:21 PM UTC 24	5485124666 ps
T14	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_clock_gating.4250478227			Oct 14 10:27:11 PM UTC 24	Oct 14 10:27:26 PM UTC 24	161891443820 ps
T217	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_alert_test.2985620678			Oct 14 10:27:27 PM UTC 24	Oct 14 10:27:29 PM UTC 24	391784668 ps
T15	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.1062136776			Oct 14 10:27:22 PM UTC 24	Oct 14 10:27:34 PM UTC 24	28214313723 ps
T16	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_polled.1411692445			Oct 14 10:26:11 PM UTC 24	Oct 14 10:27:44 PM UTC 24	165466666334 ps
T74	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_sec_cm.868011233			Oct 14 10:27:23 PM UTC 24	Oct 14 10:27:49 PM UTC 24	8179449953 ps
T119	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_smoke.1143092989			Oct 14 10:27:30 PM UTC 24	Oct 14 10:27:58 PM UTC 24	5875957613 ps
T99	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_poweron_counter.3371277141			Oct 14 10:28:16 PM UTC 24	Oct 14 10:28:23 PM UTC 24	3312718135 ps
T154	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_lowpower_counter.2983804424			Oct 14 10:27:18 PM UTC 24	Oct 14 10:28:28 PM UTC 24	33909516188 ps
T17	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_polled.1993566983			Oct 14 10:26:54 PM UTC 24	Oct 14 10:28:39 PM UTC 24	164487102319 ps
T18	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_interrupt_fixed.1504006943			Oct 14 10:27:54 PM UTC 24	Oct 14 10:28:48 PM UTC 24	170934851143 ps
T148	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_alert_test.4126756946			Oct 14 10:28:49 PM UTC 24	Oct 14 10:28:52 PM UTC 24	468817435 ps
T75	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_sec_cm.1351017272			Oct 14 10:28:40 PM UTC 24	Oct 14 10:29:03 PM UTC 24	8572961218 ps
T19	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_wakeup.3508598688			Oct 14 10:26:14 PM UTC 24	Oct 14 10:29:05 PM UTC 24	676376225067 ps
T20	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_wakeup_fixed.4168705560			Oct 14 10:26:14 PM UTC 24	Oct 14 10:29:05 PM UTC 24	598455450545 ps
T37	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_polled_fixed.2488673302			Oct 14 10:26:28 PM UTC 24	Oct 14 10:29:06 PM UTC 24	163889274268 ps
T149	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_lowpower_counter.2334396218			Oct 14 10:28:23 PM UTC 24	Oct 14 10:29:06 PM UTC 24	41762027209 ps
T38	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_polled_fixed.533423164			Oct 14 10:26:58 PM UTC 24	Oct 14 10:29:12 PM UTC 24	162096501552 ps
T150	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_smoke.821359823			Oct 14 10:28:53 PM UTC 24	Oct 14 10:29:18 PM UTC 24	5794998090 ps
T39	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_both.1422819273			Oct 14 10:26:34 PM UTC 24	Oct 14 10:29:35 PM UTC 24	177444251309 ps
T212	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_poweron_counter.2588666069			Oct 14 10:29:35 PM UTC 24	Oct 14 10:29:42 PM UTC 24	4088459347 ps
T42	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.4239657977			Oct 14 10:28:28 PM UTC 24	Oct 14 10:29:45 PM UTC 24	40756132082 ps
T173	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_interrupt.1544055415			Oct 14 10:26:28 PM UTC 24	Oct 14 10:30:05 PM UTC 24	164233271656 ps
T46	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_clock_gating.1862606145			Oct 14 10:26:14 PM UTC 24	Oct 14 10:30:11 PM UTC 24	166751652950 ps
T372	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_alert_test.721388657			Oct 14 10:30:07 PM UTC 24	Oct 14 10:30:11 PM UTC 24	496802372 ps
T120	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_both.735832152			Oct 14 10:27:11 PM UTC 24	Oct 14 10:30:22 PM UTC 24	352420778114 ps
T373	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_smoke.1397059512			Oct 14 10:30:11 PM UTC 24	Oct 14 10:30:23 PM UTC 24	5973376506 ps
T43	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.31089280			Oct 14 10:30:06 PM UTC 24	Oct 14 10:30:27 PM UTC 24	35438924430 ps
T186	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_wakeup.4193779577			Oct 14 10:27:57 PM UTC 24	Oct 14 10:30:53 PM UTC 24	197114545461 ps
T155	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_interrupt.4093735422			Oct 14 10:29:06 PM UTC 24	Oct 14 10:30:55 PM UTC 24	332857586377 ps
T52	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_fsm_reset.2999002223			Oct 14 10:26:17 PM UTC 24	Oct 14 10:30:57 PM UTC 24	69411391716 ps
T162	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_lowpower_counter.2084868637			Oct 14 10:29:44 PM UTC 24	Oct 14 10:31:11 PM UTC 24	34559231725 ps
T163	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_poweron_counter.614807479			Oct 14 10:31:06 PM UTC 24	Oct 14 10:31:21 PM UTC 24	2915346955 ps
T164	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_wakeup_fixed.3400059186			Oct 14 10:26:30 PM UTC 24	Oct 14 10:31:22 PM UTC 24	199389712241 ps
T165	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_interrupt_fixed.962248336			Oct 14 10:27:03 PM UTC 24	Oct 14 10:31:24 PM UTC 24	492991146912 ps
T50	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_fsm_reset.3973301159			Oct 14 10:27:19 PM UTC 24	Oct 14 10:31:25 PM UTC 24	72243358295 ps
T166	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_alert_test.2128634578			Oct 14 10:31:26 PM UTC 24	Oct 14 10:31:29 PM UTC 24	390248520 ps
T167	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_wakeup_fixed.239715979			Oct 14 10:26:11 PM UTC 24	Oct 14 10:31:31 PM UTC 24	398579717295 ps
T168	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_polled.1792029247			Oct 14 10:26:13 PM UTC 24	Oct 14 10:31:31 PM UTC 24	494172980025 ps
T137	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_polled.1523732884			Oct 14 10:27:34 PM UTC 24	Oct 14 10:31:31 PM UTC 24	332333183759 ps
T182	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_lowpower_counter.1842829664			Oct 14 10:31:11 PM UTC 24	Oct 14 10:31:37 PM UTC 24	39591449828 ps
T183	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_polled.22407959			Oct 14 10:28:54 PM UTC 24	Oct 14 10:31:39 PM UTC 24	164180887369 ps
T44	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.3231516768			Oct 14 10:31:22 PM UTC 24	Oct 14 10:31:41 PM UTC 24	30337448020 ps
T140	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_wakeup.2600076925			Oct 14 10:26:29 PM UTC 24	Oct 14 10:31:56 PM UTC 24	461425653826 ps
T184	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_smoke.91495168			Oct 14 10:31:30 PM UTC 24	Oct 14 10:31:57 PM UTC 24	6067503882 ps
T121	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_interrupt.2285524090			Oct 14 10:27:00 PM UTC 24	Oct 14 10:32:19 PM UTC 24	498740606476 ps
T129	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_wakeup.2604714673			Oct 14 10:30:29 PM UTC 24	Oct 14 10:32:22 PM UTC 24	181999794258 ps
T130	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_polled_fixed.458272539			Oct 14 10:29:04 PM UTC 24	Oct 14 10:32:27 PM UTC 24	328623355988 ps
T47	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_stress_all.1294853228			Oct 14 10:26:12 PM UTC 24	Oct 14 10:32:28 PM UTC 24	129801288996 ps
T131	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_poweron_counter.1204840151			Oct 14 10:32:19 PM UTC 24	Oct 14 10:32:28 PM UTC 24	4791743319 ps
T132	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_polled.4121844081			Oct 14 10:30:12 PM UTC 24	Oct 14 10:32:35 PM UTC 24	165693472996 ps
T133	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_alert_test.736440842			Oct 14 10:32:36 PM UTC 24	Oct 14 10:32:39 PM UTC 24	282532949 ps
T134	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_polled_fixed.4094284677			Oct 14 10:26:13 PM UTC 24	Oct 14 10:32:41 PM UTC 24	162041729399 ps
T135	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_lowpower_counter.546335785			Oct 14 10:32:23 PM UTC 24	Oct 14 10:32:45 PM UTC 24	31274938898 ps
T136	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_smoke.4153960918			Oct 14 10:32:40 PM UTC 24	Oct 14 10:32:54 PM UTC 24	5577343849 ps
T118	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_both.1016124544			Oct 14 10:31:58 PM UTC 24	Oct 14 10:32:47 PM UTC 24	173925043295 ps
T45	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.3464404132			Oct 14 10:32:29 PM UTC 24	Oct 14 10:32:48 PM UTC 24	28668564161 ps
T78	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_both.2764300996			Oct 14 10:28:12 PM UTC 24	Oct 14 10:32:56 PM UTC 24	191517928488 ps
T79	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_fsm_reset.127209146			Oct 14 10:26:12 PM UTC 24	Oct 14 10:33:04 PM UTC 24	81145008546 ps
T80	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_wakeup.2929206548			Oct 14 10:27:03 PM UTC 24	Oct 14 10:33:11 PM UTC 24	599038393907 ps
T81	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_polled.1766745176			Oct 14 10:32:42 PM UTC 24	Oct 14 10:33:14 PM UTC 24	166236443659 ps
T82	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_both.1208665319			Oct 14 10:26:11 PM UTC 24	Oct 14 10:33:24 PM UTC 24	501270543792 ps
T83	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_poweron_counter.2827210820			Oct 14 10:33:15 PM UTC 24	Oct 14 10:33:26 PM UTC 24	4698591761 ps
T84	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_lowpower_counter.3723854564			Oct 14 10:33:25 PM UTC 24	Oct 14 10:33:41 PM UTC 24	24165984446 ps
T85	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_alert_test.1572255579			Oct 14 10:33:46 PM UTC 24	Oct 14 10:33:48 PM UTC 24	540471219 ps
T51	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_fsm_reset.351473427			Oct 14 10:26:44 PM UTC 24	Oct 14 10:33:50 PM UTC 24	78499115672 ps
T28	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.1912185402			Oct 14 10:33:39 PM UTC 24	Oct 14 10:33:51 PM UTC 24	1443228250 ps
T243	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_stress_all.3382517496			Oct 14 10:31:25 PM UTC 24	Oct 14 10:33:51 PM UTC 24	189765866543 ps
T374	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_smoke.2739773678			Oct 14 10:33:49 PM UTC 24	Oct 14 10:34:14 PM UTC 24	5837927298 ps
T53	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_fsm_reset.3310054172			Oct 14 10:28:24 PM UTC 24	Oct 14 10:34:23 PM UTC 24	76062847285 ps
T138	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_clock_gating.3415124227			Oct 14 10:28:07 PM UTC 24	Oct 14 10:34:28 PM UTC 24	535726270093 ps
T122	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_interrupt.229840786			Oct 14 10:26:11 PM UTC 24	Oct 14 10:34:37 PM UTC 24	164735291477 ps
T141	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_wakeup.2198683013			Oct 14 10:29:06 PM UTC 24	Oct 14 10:35:23 PM UTC 24	408906918725 ps
T244	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_interrupt.4263532241			Oct 14 10:31:32 PM UTC 24	Oct 14 10:35:47 PM UTC 24	173309370464 ps
T375	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_polled_fixed.1670041699			Oct 14 10:26:11 PM UTC 24	Oct 14 10:35:51 PM UTC 24	159370674904 ps
T376	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_poweron_counter.3341011676			Oct 14 10:35:48 PM UTC 24	Oct 14 10:35:53 PM UTC 24	5214061766 ps
T123	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_stress_all.1845503864			Oct 14 10:26:20 PM UTC 24	Oct 14 10:35:59 PM UTC 24	394484970816 ps
T29	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.561861462			Oct 14 10:35:56 PM UTC 24	Oct 14 10:36:14 PM UTC 24	7101006722 ps
T377	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_alert_test.3384393702			Oct 14 10:36:15 PM UTC 24	Oct 14 10:36:17 PM UTC 24	443486660 ps
T378	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_lowpower_counter.1084880930			Oct 14 10:35:51 PM UTC 24	Oct 14 10:36:17 PM UTC 24	25962475525 ps
T304	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_interrupt_fixed.936725689			Oct 14 10:26:14 PM UTC 24	Oct 14 10:36:19 PM UTC 24	489609836232 ps
T139	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_interrupt.3554843600			Oct 14 10:33:51 PM UTC 24	Oct 14 10:36:21 PM UTC 24	169771033850 ps
T379	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_smoke.604623658			Oct 14 10:36:18 PM UTC 24	Oct 14 10:36:27 PM UTC 24	5718128489 ps
T240	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_both.3466405200			Oct 14 10:26:15 PM UTC 24	Oct 14 10:36:34 PM UTC 24	162413858177 ps
T236	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_clock_gating.3659492662			Oct 14 10:34:38 PM UTC 24	Oct 14 10:36:55 PM UTC 24	161562660596 ps
T48	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_stress_all.2134534687			Oct 14 10:27:22 PM UTC 24	Oct 14 10:36:57 PM UTC 24	89139186039 ps
T151	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_stress_all.1738781119			Oct 14 10:28:29 PM UTC 24	Oct 14 10:36:58 PM UTC 24	558298904320 ps
T380	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_poweron_counter.3748657352			Oct 14 10:36:59 PM UTC 24	Oct 14 10:37:10 PM UTC 24	4686257012 ps
T381	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_polled_fixed.3359046638			Oct 14 10:27:45 PM UTC 24	Oct 14 10:37:16 PM UTC 24	493656262978 ps
T251	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_both.2167409070			Oct 14 10:33:11 PM UTC 24	Oct 14 10:37:25 PM UTC 24	163735527892 ps
T185	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_interrupt_fixed.598388173			Oct 14 10:36:21 PM UTC 24	Oct 14 10:37:30 PM UTC 24	330135964828 ps
T255	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.2423674172			Oct 14 10:37:26 PM UTC 24	Oct 14 10:37:38 PM UTC 24	3138046920 ps
T382	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_interrupt_fixed.260591236			Oct 14 10:26:11 PM UTC 24	Oct 14 10:37:41 PM UTC 24	486930091752 ps
T383	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_alert_test.2773895186			Oct 14 10:37:39 PM UTC 24	Oct 14 10:37:43 PM UTC 24	454642726 ps
T124	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_clock_gating.2619154613			Oct 14 10:33:04 PM UTC 24	Oct 14 10:38:07 PM UTC 24	524029351844 ps
T142	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_wakeup.3914486751			Oct 14 10:32:55 PM UTC 24	Oct 14 10:38:10 PM UTC 24	374713264693 ps
T194	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_smoke.2691050566			Oct 14 10:37:42 PM UTC 24	Oct 14 10:38:10 PM UTC 24	6005691937 ps
T195	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_polled_fixed.1939116475			Oct 14 10:31:32 PM UTC 24	Oct 14 10:38:13 PM UTC 24	495603516723 ps
T152	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_stress_all.3125018550			Oct 14 10:33:42 PM UTC 24	Oct 14 10:38:19 PM UTC 24	377043289796 ps
T196	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_lowpower_counter.1723165797			Oct 14 10:37:11 PM UTC 24	Oct 14 10:38:30 PM UTC 24	36052021747 ps
T197	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_wakeup.942857248			Oct 14 10:31:40 PM UTC 24	Oct 14 10:38:47 PM UTC 24	361016568703 ps
T198	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_interrupt_fixed.2770807591			Oct 14 10:26:29 PM UTC 24	Oct 14 10:39:04 PM UTC 24	330823236828 ps
T125	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_both.2077045367			Oct 14 10:36:58 PM UTC 24	Oct 14 10:39:16 PM UTC 24	345117348012 ps
T199	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_poweron_counter.520451370			Oct 14 10:39:05 PM UTC 24	Oct 14 10:39:20 PM UTC 24	3626371574 ps
T200	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_fsm_reset.532287174			Oct 14 10:33:27 PM UTC 24	Oct 14 10:39:27 PM UTC 24	88622757827 ps
T153	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_both.485643177			Oct 14 10:35:24 PM UTC 24	Oct 14 10:39:51 PM UTC 24	197367392353 ps
T384	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_wakeup_fixed.3088457299			Oct 14 10:29:07 PM UTC 24	Oct 14 10:39:57 PM UTC 24	203658319772 ps
T247	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.637274256			Oct 14 10:39:28 PM UTC 24	Oct 14 10:39:58 PM UTC 24	244092818825 ps
T223	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_fsm_reset.1412337342			Oct 14 10:29:46 PM UTC 24	Oct 14 10:40:01 PM UTC 24	128687622719 ps
T385	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_alert_test.197578810			Oct 14 10:39:57 PM UTC 24	Oct 14 10:40:02 PM UTC 24	524007539 ps
T386	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_polled_fixed.3978303005			Oct 14 10:38:08 PM UTC 24	Oct 14 10:40:08 PM UTC 24	166690537817 ps
T387	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_smoke.223036741			Oct 14 10:39:59 PM UTC 24	Oct 14 10:40:09 PM UTC 24	6107406359 ps
T49	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_fsm_reset.1628197081			Oct 14 10:32:28 PM UTC 24	Oct 14 10:40:49 PM UTC 24	125166168574 ps
T388	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_lowpower_counter.3457788903			Oct 14 10:39:17 PM UTC 24	Oct 14 10:40:50 PM UTC 24	37473941340 ps
T256	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_polled.3883179314			Oct 14 10:33:51 PM UTC 24	Oct 14 10:41:18 PM UTC 24	167750584680 ps
T389	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_polled_fixed.1659258371			Oct 14 10:33:51 PM UTC 24	Oct 14 10:41:21 PM UTC 24	164788480127 ps
T390	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_interrupt_fixed.2329388554			Oct 14 10:31:38 PM UTC 24	Oct 14 10:41:36 PM UTC 24	163361731390 ps
T391	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_poweron_counter.2862575363			Oct 14 10:41:21 PM UTC 24	Oct 14 10:41:41 PM UTC 24	4073789852 ps
T143	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_interrupt.161018970			Oct 14 10:27:50 PM UTC 24	Oct 14 10:41:44 PM UTC 24	326000758864 ps
T30	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.4134728086			Oct 14 10:41:45 PM UTC 24	Oct 14 10:41:57 PM UTC 24	4589443131 ps
T222	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_fsm_reset.1740234126			Oct 14 10:35:53 PM UTC 24	Oct 14 10:42:09 PM UTC 24	63624327663 ps
T392	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_alert_test.2658601953			Oct 14 10:42:10 PM UTC 24	Oct 14 10:42:12 PM UTC 24	492890215 ps
T237	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_polled.4007467761			Oct 14 10:36:18 PM UTC 24	Oct 14 10:42:18 PM UTC 24	500425388675 ps
T393	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_smoke.2803121606			Oct 14 10:42:13 PM UTC 24	Oct 14 10:42:28 PM UTC 24	5879636444 ps
T394	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_wakeup_fixed.2546898685			Oct 14 10:27:59 PM UTC 24	Oct 14 10:42:28 PM UTC 24	605775308628 ps
T395	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_polled_fixed.1711320353			Oct 14 10:30:15 PM UTC 24	Oct 14 10:42:32 PM UTC 24	326280694213 ps
T238	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_interrupt.1155947286			Oct 14 10:26:14 PM UTC 24	Oct 14 10:42:38 PM UTC 24	326091653084 ps
T144	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_polled.4147642682			Oct 14 10:31:32 PM UTC 24	Oct 14 10:43:13 PM UTC 24	319589047342 ps
T396	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_lowpower_counter.1173124312			Oct 14 10:41:37 PM UTC 24	Oct 14 10:43:18 PM UTC 24	43830855009 ps
T242	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_clock_gating.3744731271			Oct 14 10:30:56 PM UTC 24	Oct 14 10:43:19 PM UTC 24	571341877415 ps
T397	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_wakeup_fixed.2840250802			Oct 14 10:40:50 PM UTC 24	Oct 14 10:43:23 PM UTC 24	613685212532 ps
T398	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_wakeup_fixed.664813127			Oct 14 10:38:21 PM UTC 24	Oct 14 10:43:31 PM UTC 24	600527036051 ps
T169	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_wakeup.980192073			Oct 14 10:36:27 PM UTC 24	Oct 14 10:43:33 PM UTC 24	541847809933 ps
T399	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_poweron_counter.3909585148			Oct 14 10:43:24 PM UTC 24	Oct 14 10:43:35 PM UTC 24	3900515567 ps
T400	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_wakeup_fixed.3369613675			Oct 14 10:36:35 PM UTC 24	Oct 14 10:43:58 PM UTC 24	386093924807 ps
T252	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_both.2577727342			Oct 14 10:29:18 PM UTC 24	Oct 14 10:43:58 PM UTC 24	388523982796 ps
T401	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_alert_test.1765032700			Oct 14 10:43:59 PM UTC 24	Oct 14 10:44:02 PM UTC 24	337400307 ps
T170	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.1686703490			Oct 14 10:43:36 PM UTC 24	Oct 14 10:44:11 PM UTC 24	18979434480 ps
T402	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_smoke.1442377555			Oct 14 10:44:03 PM UTC 24	Oct 14 10:44:29 PM UTC 24	5823707560 ps
T403	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_lowpower_counter.3984866897			Oct 14 10:43:32 PM UTC 24	Oct 14 10:44:29 PM UTC 24	35458702794 ps
T272	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_wakeup.19886694			Oct 14 10:26:11 PM UTC 24	Oct 14 10:44:30 PM UTC 24	369307819235 ps
T404	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_fsm_reset.4264698170			Oct 14 10:37:17 PM UTC 24	Oct 14 10:44:39 PM UTC 24	81198280409 ps
T257	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_interrupt.249354739			Oct 14 10:42:28 PM UTC 24	Oct 14 10:44:45 PM UTC 24	168599738306 ps
T54	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_stress_all.3775799825			Oct 14 10:32:29 PM UTC 24	Oct 14 10:45:07 PM UTC 24	133180713229 ps
T126	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_clock_gating.1100850456			Oct 14 10:26:33 PM UTC 24	Oct 14 10:45:15 PM UTC 24	361001904281 ps
T405	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_poweron_counter.2246050041			Oct 14 10:45:10 PM UTC 24	Oct 14 10:45:33 PM UTC 24	4947008329 ps
T241	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_polled.542915435			Oct 14 10:37:43 PM UTC 24	Oct 14 10:45:37 PM UTC 24	329707602536 ps
T239	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_interrupt.3677230319			Oct 14 10:36:21 PM UTC 24	Oct 14 10:45:46 PM UTC 24	168819892485 ps
T406	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_alert_test.1840312673			Oct 14 10:45:47 PM UTC 24	Oct 14 10:45:49 PM UTC 24	427470048 ps
T407	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.1072823777			Oct 14 10:45:34 PM UTC 24	Oct 14 10:45:52 PM UTC 24	1476391886 ps
T219	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_fsm_reset.546364425			Oct 14 10:39:21 PM UTC 24	Oct 14 10:45:55 PM UTC 24	105765543208 ps
T408	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_smoke.3044860477			Oct 14 10:45:50 PM UTC 24	Oct 14 10:45:57 PM UTC 24	5622225505 ps
T145	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_clock_gating.1664751244			Oct 14 10:38:31 PM UTC 24	Oct 14 10:46:06 PM UTC 24	321884548345 ps
T146	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_wakeup.3492407244			Oct 14 10:42:38 PM UTC 24	Oct 14 10:46:07 PM UTC 24	351148925801 ps
T409	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_lowpower_counter.642945889			Oct 14 10:45:15 PM UTC 24	Oct 14 10:46:08 PM UTC 24	27131884709 ps
T245	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_polled.1642917014			Oct 14 10:44:12 PM UTC 24	Oct 14 10:46:23 PM UTC 24	164415289519 ps
T410	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_wakeup_fixed.2939730207			Oct 14 10:34:30 PM UTC 24	Oct 14 10:46:46 PM UTC 24	411936358232 ps
T213	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_clock_gating.2120305221			Oct 14 10:45:05 PM UTC 24	Oct 14 10:46:47 PM UTC 24	588564946447 ps
T411	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_interrupt_fixed.3492553847			Oct 14 10:42:33 PM UTC 24	Oct 14 10:46:52 PM UTC 24	326424620250 ps
T171	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_clock_gating.395929402			Oct 14 10:29:13 PM UTC 24	Oct 14 10:46:55 PM UTC 24	492929431976 ps
T412	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_poweron_counter.1025530135			Oct 14 10:46:48 PM UTC 24	Oct 14 10:46:58 PM UTC 24	3555997946 ps
T147	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_wakeup.2227063919			Oct 14 10:34:23 PM UTC 24	Oct 14 10:47:00 PM UTC 24	194677305455 ps
T300	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_clock_gating.1389387508			Oct 14 10:43:20 PM UTC 24	Oct 14 10:47:02 PM UTC 24	169813929597 ps
T413	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_alert_test.2441667422			Oct 14 10:47:03 PM UTC 24	Oct 14 10:47:06 PM UTC 24	354043791 ps
T281	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_both.3109034167			Oct 14 10:30:58 PM UTC 24	Oct 14 10:47:07 PM UTC 24	339694202661 ps
T76	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.1082035113			Oct 14 10:46:59 PM UTC 24	Oct 14 10:47:08 PM UTC 24	7641168750 ps
T258	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_polled.1406290118			Oct 14 10:26:27 PM UTC 24	Oct 14 10:47:09 PM UTC 24	493738268097 ps
T414	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_stress_all.2904196152			Oct 14 10:47:01 PM UTC 24	Oct 14 10:47:12 PM UTC 24	8064296714 ps
T415	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_smoke.1360130728			Oct 14 10:47:07 PM UTC 24	Oct 14 10:47:15 PM UTC 24	5825910949 ps
T262	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_interrupt.2625453064			Oct 14 10:40:09 PM UTC 24	Oct 14 10:47:21 PM UTC 24	170113792706 ps
T416	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_polled_fixed.3807741609			Oct 14 10:40:03 PM UTC 24	Oct 14 10:47:22 PM UTC 24	163180784967 ps
T127	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_both.3054891980			Oct 14 10:38:48 PM UTC 24	Oct 14 10:47:23 PM UTC 24	526002794866 ps
T417	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_interrupt_fixed.1559701329			Oct 14 10:40:10 PM UTC 24	Oct 14 10:47:36 PM UTC 24	167193098012 ps
T128	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_interrupt.3827430684			Oct 14 10:32:47 PM UTC 24	Oct 14 10:47:36 PM UTC 24	336121575391 ps
T283	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_wakeup.3622525384			Oct 14 10:38:14 PM UTC 24	Oct 14 10:47:41 PM UTC 24	379102812652 ps
T418	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_poweron_counter.2172385996			Oct 14 10:47:37 PM UTC 24	Oct 14 10:47:44 PM UTC 24	2859065593 ps
T246	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_interrupt.3787633612			Oct 14 10:30:22 PM UTC 24	Oct 14 10:47:48 PM UTC 24	490502099121 ps
T419	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.3820516315			Oct 14 10:47:46 PM UTC 24	Oct 14 10:48:01 PM UTC 24	2920445930 ps
T156	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_both.4130055752			Oct 14 10:41:18 PM UTC 24	Oct 14 10:48:03 PM UTC 24	488793164248 ps
T420	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_alert_test.2753054067			Oct 14 10:48:02 PM UTC 24	Oct 14 10:48:04 PM UTC 24	309996354 ps
T421	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_smoke.1302602250			Oct 14 10:48:04 PM UTC 24	Oct 14 10:48:09 PM UTC 24	6031381908 ps
T422	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_interrupt_fixed.2310028769			Oct 14 10:34:14 PM UTC 24	Oct 14 10:48:18 PM UTC 24	332647081178 ps
T201	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_both.2406639276			Oct 14 10:43:21 PM UTC 24	Oct 14 10:48:18 PM UTC 24	331151706171 ps
T205	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_fsm_reset.2503371311			Oct 14 10:31:22 PM UTC 24	Oct 14 10:48:23 PM UTC 24	138470839568 ps
T206	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_lowpower_counter.4165887949			Oct 14 10:47:37 PM UTC 24	Oct 14 10:48:24 PM UTC 24	27517431646 ps
T174	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_clock_gating.2584369301			Oct 14 10:31:56 PM UTC 24	Oct 14 10:48:26 PM UTC 24	366379425954 ps
T172	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_interrupt_fixed.2768905279			Oct 14 10:46:07 PM UTC 24	Oct 14 10:48:32 PM UTC 24	320047304963 ps
T207	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_wakeup.816844830			Oct 14 10:40:49 PM UTC 24	Oct 14 10:48:36 PM UTC 24	366555699286 ps
T208	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_poweron_counter.4029211542			Oct 14 10:48:33 PM UTC 24	Oct 14 10:48:49 PM UTC 24	3017429266 ps
T209	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_wakeup_fixed.3948051829			Oct 14 10:31:42 PM UTC 24	Oct 14 10:48:49 PM UTC 24	410288694289 ps
T210	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_lowpower_counter.1469875163			Oct 14 10:48:37 PM UTC 24	Oct 14 10:49:07 PM UTC 24	39630165024 ps
T31	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.3914548345			Oct 14 10:48:50 PM UTC 24	Oct 14 10:49:10 PM UTC 24	4233315680 ps
T423	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_polled_fixed.3910412053			Oct 14 10:47:09 PM UTC 24	Oct 14 10:49:12 PM UTC 24	164970634133 ps
T424	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_alert_test.2795143210			Oct 14 10:49:11 PM UTC 24	Oct 14 10:49:13 PM UTC 24	433082958 ps
T309	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_both.4134157904			Oct 14 10:45:08 PM UTC 24	Oct 14 10:49:18 PM UTC 24	167133450462 ps
T425	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_lowpower_counter.2113896766			Oct 14 10:46:53 PM UTC 24	Oct 14 10:49:23 PM UTC 24	39750229454 ps
T426	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_smoke.333492668			Oct 14 10:49:13 PM UTC 24	Oct 14 10:49:25 PM UTC 24	5639302276 ps
T227	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_fsm_reset.3132180170			Oct 14 10:41:42 PM UTC 24	Oct 14 10:49:39 PM UTC 24	80284145432 ps
T427	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_wakeup_fixed.2978719264			Oct 14 10:43:14 PM UTC 24	Oct 14 10:49:42 PM UTC 24	603392433420 ps
T157	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_polled.964025307			Oct 14 10:47:08 PM UTC 24	Oct 14 10:49:44 PM UTC 24	332421732898 ps
T428	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_interrupt_fixed.1174721091			Oct 14 10:29:06 PM UTC 24	Oct 14 10:50:01 PM UTC 24	492049859975 ps
T429	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_wakeup_fixed.1914062366			Oct 14 10:27:04 PM UTC 24	Oct 14 10:50:09 PM UTC 24	401411862701 ps
T430	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_wakeup_fixed.2473726401			Oct 14 10:44:46 PM UTC 24	Oct 14 10:50:26 PM UTC 24	409005411023 ps
T431	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_poweron_counter.1887596595			Oct 14 10:50:09 PM UTC 24	Oct 14 10:50:29 PM UTC 24	4343228419 ps
T432	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_polled_fixed.1942373199			Oct 14 10:48:10 PM UTC 24	Oct 14 10:50:44 PM UTC 24	159240850885 ps
T270	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.1758252620			Oct 14 10:50:46 PM UTC 24	Oct 14 10:51:03 PM UTC 24	21135351414 ps
T433	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_polled_fixed.92711287			Oct 14 10:49:19 PM UTC 24	Oct 14 10:51:19 PM UTC 24	162779774979 ps
T434	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_alert_test.1507286141			Oct 14 10:51:19 PM UTC 24	Oct 14 10:51:21 PM UTC 24	434160868 ps
T435	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_interrupt_fixed.2354883137			Oct 14 10:47:13 PM UTC 24	Oct 14 10:51:23 PM UTC 24	333323591442 ps
T436	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_smoke.2733666953			Oct 14 10:51:22 PM UTC 24	Oct 14 10:51:27 PM UTC 24	5915599004 ps
T437	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_polled_fixed.512806826			Oct 14 10:45:56 PM UTC 24	Oct 14 10:51:36 PM UTC 24	490914815217 ps
T261	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_stress_all.2787403317			Oct 14 10:41:58 PM UTC 24	Oct 14 10:51:42 PM UTC 24	502621347667 ps
T260	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_clock_gating.3716264508			Oct 14 10:49:45 PM UTC 24	Oct 14 10:51:48 PM UTC 24	164787799175 ps
T248	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_both.3061957647			Oct 14 10:46:47 PM UTC 24	Oct 14 10:51:51 PM UTC 24	577320944523 ps
T268	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_stress_all.461043573			Oct 14 10:49:07 PM UTC 24	Oct 14 10:52:06 PM UTC 24	210159378771 ps
T438	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_polled.3646690310			Oct 14 10:42:19 PM UTC 24	Oct 14 10:52:15 PM UTC 24	168066067742 ps
T214	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_interrupt.3691129999			Oct 14 10:47:10 PM UTC 24	Oct 14 10:52:17 PM UTC 24	486461270485 ps
T233	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_stress_all.2804197052			Oct 14 10:43:59 PM UTC 24	Oct 14 10:52:18 PM UTC 24	135911934173 ps
T292	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_both.3556056531			Oct 14 10:52:16 PM UTC 24	Oct 14 10:52:39 PM UTC 24	158461375370 ps
T439	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_poweron_counter.4030029705			Oct 14 10:52:18 PM UTC 24	Oct 14 10:52:40 PM UTC 24	4874585756 ps
T302	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_polled.3201341678			Oct 14 10:45:53 PM UTC 24	Oct 14 10:52:40 PM UTC 24	487851366692 ps
T440	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.2135264290			Oct 14 10:52:40 PM UTC 24	Oct 14 10:52:46 PM UTC 24	832385817 ps
T441	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_alert_test.593377430			Oct 14 10:52:46 PM UTC 24	Oct 14 10:52:50 PM UTC 24	519375301 ps
T442	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_wakeup_fixed.14769468			Oct 14 10:30:54 PM UTC 24	Oct 14 10:52:52 PM UTC 24	395143895381 ps
T232	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_stress_all.1410488831			Oct 14 10:45:38 PM UTC 24	Oct 14 10:53:07 PM UTC 24	279330351706 ps
T443	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_lowpower_counter.1117482826			Oct 14 10:50:26 PM UTC 24	Oct 14 10:53:07 PM UTC 24	39502454302 ps
T444	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_smoke.2456961126			Oct 14 10:52:51 PM UTC 24	Oct 14 10:53:10 PM UTC 24	5737421673 ps
T284	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_clock_gating.3497304542			Oct 14 10:52:07 PM UTC 24	Oct 14 10:53:30 PM UTC 24	327537295280 ps
T332	/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_wakeup.3723063250			Oct 14 10:48:19 PM UTC 24	Oct 14 10:53:39 PM UTC 24	174444554425 ps