Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22968

1

T2

20

T3

20

T4

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19492

1

T2

20

T3

20

T4

1

auto[ADC_CTRL_FILTER_COND_OUT]

3476

1

T10

3

T15

8

T16

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16988

1

T2

20

T3

20

T4

1

auto[1]

5980

1

T10

8

T16

1

T18

5

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19141

1

T2

20

T3

20

T4

1

auto[1]

3827

1

T10

6

T11

1

T25

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	263	1			T141	16		T244	12		T124	2
values[0]	39	1			T168	1		T142	15		T353	8
values[1]	692	1			T10	5		T19	5		T186	6
values[2]	617	1			T43	11		T137	1		T81	1
values[3]	742	1			T10	3		T19	24		T42	7
values[4]	448	1			T11	2		T121	8		T80	14
values[5]	573	1			T13	4		T118	24		T138	10
values[6]	628	1			T16	1		T39	35		T173	3
values[7]	679	1			T15	8		T155	10		T168	1
values[8]	3234	1			T18	5		T20	28		T37	1
values[9]	1037	1			T14	2		T17	1		T120	18
minimum	14016	1			T2	20		T3	20		T4	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	696	1			T19	5		T43	11		T186	6
values[1]	686	1			T19	15		T121	12		T81	1
values[2]	659	1			T10	3		T11	2		T19	9
values[3]	478	1			T13	4		T121	8		T118	24
values[4]	562	1			T138	10		T236	27		T151	39
values[5]	709	1			T16	1		T173	3		T183	1
values[6]	3203	1			T15	8		T18	5		T20	28
values[7]	618	1			T120	17		T78	17		T80	11
values[8]	1057	1			T14	2		T17	1		T120	18
values[9]	119	1			T141	16		T232	15		T319	9
minimum	14181	1			T2	20		T3	20		T4	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18746

1

T2

20

T3

20

T4

1

auto[1]

4222

1

T10

1

T15

2

T19

26

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T19	5		T186	6		T137	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T43	9		T168	1		T82	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T237	2		T238	1		T239	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T19	15		T121	1		T81	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T11	1		T19	9		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T10	2		T42	6		T46	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T13	3		T121	1		T80	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T118	15		T138	1		T240	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T30	1		T170	1		T241	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T138	6		T236	15		T151	24
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T183	1		T122	1		T153	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T16	1		T173	1		T140	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1741	1			T18	1		T20	28		T37	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T15	6		T39	11		T82	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T120	9		T78	10		T242	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T80	11		T243	1		T123	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	320	1			T14	1		T17	1		T120	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T45	8		T244	1		T142	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T232	12		T319	7		T325	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T141	16		T158	1		T33	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13934	1			T2	20		T3	20		T4	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T127	9		T314	1		T289	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T128	13		T246	1		T174	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T43	2		T82	2		T123	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T238	10		T239	1		T171	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T121	11		T82	15		T201	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T11	1		T247	1		T171	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T10	1		T42	1		T46	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T13	1		T121	7		T216	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T118	9		T138	1		T240	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T248	1		T249	11		T250	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T138	4		T236	12		T151	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T122	11		T153	10		T242	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T173	2		T251	12		T213	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1065	1			T18	4		T155	9		T165	21
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T15	2		T39	24		T82	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T120	8		T78	7		T242	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T243	9		T123	8		T252	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T14	1		T120	8		T44	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T45	3		T244	11		T145	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T232	3		T319	2		T325	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T254	11		T354	8		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T10	5		T25	2		T13	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T127	10		T203	13		T235	7

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T124	1		T157	1		T232	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T141	16		T244	1		T145	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T353	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T168	1		T142	15		T235	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T10	3		T19	5		T186	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T127	10		T128	1		T283	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T137	1		T237	2		T146	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T43	9		T81	1		T82	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T19	9		T137	1		T238	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T10	2		T19	15		T42	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T11	1		T121	1		T80	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T138	1		T240	4		T256	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T13	3		T30	1		T170	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T118	15		T138	6		T236	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T183	1		T122	1		T242	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T16	1		T39	11		T173	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T155	1		T168	1		T197	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T15	6		T82	1		T124	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1736	1			T18	1		T20	28		T37	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T80	11		T123	13		T197	22
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T14	1		T17	1		T120	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T45	8		T243	1		T142	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13898	1			T2	20		T3	20		T4	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T124	1		T232	3		T267	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T244	11		T145	9		T305	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T353	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T235	7		T259	4		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T10	2		T174	11		T260	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T127	10		T174	8		T274	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T128	13		T246	1		T261	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T43	2		T82	17		T123	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T238	10		T239	1		T171	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T10	1		T42	1		T46	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T11	1		T121	7		T247	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T138	1		T240	3		T262	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T13	1		T249	11		T250	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T118	9		T138	4		T236	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T122	11		T242	2		T257	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T39	24		T173	2		T251	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T155	9		T125	7		T153	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T15	2		T82	4		T124	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1057	1			T18	4		T120	8		T165	21
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T123	8		T252	10		T55	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T14	1		T120	8		T44	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T45	3		T243	9		T284	18
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T10	3		T25	2		T13	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T19	1		T186	1		T137	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T43	8		T168	1		T82	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T237	2		T238	11		T239	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T19	1		T121	12		T81	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T11	2		T19	1		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T10	3		T42	6		T46	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T13	4		T121	8		T80	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T118	10		T138	2		T240	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T30	1		T170	1		T241	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T138	5		T236	13		T151	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T183	1		T122	12		T153	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T16	1		T173	3		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1419	1			T18	5		T20	3		T37	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T15	6		T39	25		T82	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T120	9		T78	8		T242	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T80	1		T243	10		T123	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	316	1			T14	2		T17	1		T120	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T45	8		T244	12		T142	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T232	4		T319	7		T325	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T141	1		T158	1		T33	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14082	1			T2	20		T3	20		T4	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T127	11		T314	1		T289	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T19	4		T186	5		T80	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T43	3		T123	9		T142	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T146	14		T171	4		T266	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T19	14		T82	9		T201	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T19	8		T247	1		T171	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T42	1		T46	14		T140	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T80	13		T141	2		T265	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T118	14		T240	3		T201	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T248	1		T249	13		T250	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T138	5		T236	14		T151	22
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T153	10		T242	2		T126	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T140	4		T251	14		T156	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1387	1			T20	25		T164	15		T167	22
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T15	2		T39	10		T145	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T120	8		T78	9		T242	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T80	10		T123	12		T197	21
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T120	9		T44	1		T129	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T45	3		T142	13		T169	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T232	11		T319	2		T311	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T141	15		T190	7		T355	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T10	1		T260	9		T216	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T127	8		T289	12		T356	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T124	2		T157	1		T232	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T141	1		T244	12		T145	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T353	8		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T168	1		T142	1		T235	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T10	4		T19	1		T186	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T127	12		T128	1		T283	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T137	1		T237	2		T146	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T43	8		T81	1		T82	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T19	1		T137	1		T238	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T10	3		T19	1		T42	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T11	2		T121	8		T80	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T138	2		T240	4		T256	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T13	4		T30	1		T170	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T118	10		T138	5		T236	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T183	1		T122	12		T242	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T16	1		T39	25		T173	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T155	10		T168	1		T197	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T15	6		T82	5		T124	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1411	1			T18	5		T20	3		T37	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T80	1		T123	9		T197	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T14	2		T17	1		T120	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T45	8		T243	10		T142	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14016	1			T2	20		T3	20		T4	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T232	11		T267	4		T319	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T141	15		T145	7		T305	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T142	14		T235	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T10	1		T19	4		T186	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T127	8		T283	12		T156	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T146	14		T266	1		T333	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T43	3		T82	9		T123	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T19	8		T171	7		T267	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T19	14		T42	1		T46	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T80	13		T141	2		T247	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T240	3		T201	13		T159	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T249	13		T250	5		T179	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T118	14		T138	5		T236	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T242	2		T207	19		T248	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T39	10		T140	4		T251	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T197	9		T125	8		T153	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T15	2		T145	6		T127	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1382	1			T20	25		T120	8		T164	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T80	10		T123	12		T197	21
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T120	9		T44	1		T129	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T45	3		T142	13		T169	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18746

1

T2

20

T3

20

T4

1

auto[1]

auto[0]

4222

1

T10

1

T15

2

T19

26