Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22968

1

T2

20

T3

20

T4

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

16980

1

T2

20

T3

20

T4

1

auto[ADC_CTRL_FILTER_COND_OUT]

5988

1

T10

5

T11

2

T13

4

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17366

1

T2

20

T3

20

T4

1

auto[1]

5602

1

T10

5

T13

4

T17

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19141

1

T2

20

T3

20

T4

1

auto[1]

3827

1

T10

6

T11

1

T25

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	140	1			T81	1		T240	7		T124	2
values[0]	58	1			T146	15		T281	29		T36	12
values[1]	718	1			T14	2		T15	8		T39	35
values[2]	712	1			T17	1		T168	1		T121	13
values[3]	588	1			T19	14		T120	17		T155	11
values[4]	856	1			T42	7		T186	6		T155	10
values[5]	690	1			T13	4		T78	17		T29	1
values[6]	657	1			T168	2		T121	8		T129	13
values[7]	606	1			T10	3		T80	11		T151	5
values[8]	483	1			T10	5		T11	2		T19	15
values[9]	3444	1			T16	1		T18	5		T20	28
minimum	14016	1			T2	20		T3	20		T4	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	720	1			T14	2		T39	35		T120	18
values[1]	3070	1			T17	1		T18	5		T19	5
values[2]	703	1			T19	9		T155	11		T137	1
values[3]	752	1			T42	7		T186	6		T155	10
values[4]	825	1			T13	4		T168	1		T121	8
values[5]	564	1			T10	3		T168	1		T129	13
values[6]	555	1			T183	1		T80	11		T151	5
values[7]	601	1			T10	5		T11	2		T16	1
values[8]	784	1			T46	20		T121	12		T80	14
values[9]	129	1			T173	3		T256	1		T76	1
minimum	14265	1			T2	20		T3	20		T4	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18746

1

T2

20

T3

20

T4

1

auto[1]

4222

1

T10

1

T15

2

T19

26

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T120	10		T43	9		T82	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T14	1		T39	11		T82	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T19	5		T120	9		T126	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1741	1			T17	1		T18	1		T20	28
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T140	17		T236	15		T213	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T19	9		T155	1		T137	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T42	6		T186	6		T137	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T155	1		T82	10		T141	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T78	10		T122	1		T255	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T13	3		T168	1		T121	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T10	2		T129	13		T124	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T168	1		T132	1		T80	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T183	1		T151	5		T237	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T80	11		T124	1		T237	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T151	19		T197	10		T145	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T10	3		T11	1		T16	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T121	1		T245	1		T171	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T46	15		T80	14		T81	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T256	1		T268	2		T293	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T173	1		T76	1		T127	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13963	1			T2	20		T3	20		T4	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T15	6		T243	1		T152	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T120	8		T43	2		T82	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T14	1		T39	24		T82	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T120	8		T126	15		T262	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1070	1			T18	4		T165	21		T121	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T236	12		T213	1		T171	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T155	10		T44	1		T118	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T42	1		T239	1		T261	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T155	9		T82	15		T175	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T78	7		T122	11		T125	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T13	1		T121	7		T152	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T10	1		T124	14		T247	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T139	12		T143	2		T267	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T242	2		T171	6		T156	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T124	1		T281	3		T176	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T151	15		T145	9		T213	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T10	2		T11	1		T153	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T121	11		T171	9		T246	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T46	5		T244	11		T240	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T268	3		T293	2		T203	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T173	2		T127	10		T216	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T10	3		T25	2		T13	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T15	2		T243	9		T281	13

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T339	1		T285	5		T357	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T81	1		T240	4		T124	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T146	15		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T281	16		T36	1		T326	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T120	10		T43	9		T82	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T14	1		T15	6		T39	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T251	15		T126	15		T262	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T17	1		T168	1		T121	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T19	5		T120	9		T140	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T19	9		T155	1		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T42	6		T186	6		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T155	1		T118	15		T82	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T78	10		T255	3		T125	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T13	3		T29	1		T142	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T129	13		T122	1		T247	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T168	2		T121	1		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T10	2		T151	5		T124	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T80	11		T124	1		T143	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T183	1		T197	10		T145	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T10	3		T11	1		T19	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T121	1		T151	19		T256	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1867	1			T16	1		T18	1		T20	28
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13898	1			T2	20		T3	20		T4	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T285	3		T203	13		T358	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T240	3		T124	1		T127	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T281	13		T36	11		T326	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T120	8		T43	2		T82	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T14	1		T15	2		T39	24
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T251	12		T126	15		T262	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T121	12		T45	3		T82	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T120	8		T236	12		T213	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T155	10		T44	1		T151	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T42	1		T239	1		T248	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T155	9		T118	9		T82	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T78	7		T125	7		T261	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T13	1		T145	8		T174	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T122	11		T247	2		T143	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T121	7		T139	12		T152	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T10	1		T124	14		T242	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T124	1		T143	2		T267	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T145	9		T156	2		T158	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T10	2		T11	1		T153	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T121	11		T151	15		T213	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1104	1			T18	4		T173	2		T46	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T10	3		T25	2		T13	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T120	9		T43	8		T82	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T14	2		T39	25		T82	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T19	1		T120	9		T126	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1431	1			T17	1		T18	5		T20	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T140	2		T236	13		T213	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T19	1		T155	11		T137	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T42	6		T186	1		T137	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T155	10		T82	16		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T78	8		T122	12		T255	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T13	4		T168	1		T121	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T10	3		T129	1		T124	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T168	1		T132	1		T80	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T183	1		T151	1		T237	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T80	1		T124	2		T237	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T151	16		T197	1		T145	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T10	4		T11	2		T16	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T121	12		T245	1		T171	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T46	6		T80	1		T81	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T256	1		T268	4		T293	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T173	3		T76	1		T127	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14076	1			T2	20		T3	20		T4	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T15	6		T243	10		T152	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T120	9		T43	3		T251	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T39	10		T123	12		T169	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T19	4		T120	8		T126	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1380	1			T20	25		T164	15		T167	22
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T140	15		T236	14		T171	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T19	8		T44	1		T118	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T42	1		T186	5		T207	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T82	9		T141	15		T197	21
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T78	9		T125	8		T242	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T142	13		T272	15		T145	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T129	12		T124	13		T247	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T80	7		T332	1		T267	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T151	4		T242	6		T171	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T80	10		T146	7		T282	22
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T151	18		T197	9		T145	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T10	1		T19	14		T141	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T171	3		T232	11		T265	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T46	14		T80	13		T240	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T268	1		T323	6		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T127	8		T216	6		T296	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T138	11		T123	9		T146	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T15	2		T281	15		T270	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T339	1		T285	4		T357	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T81	1		T240	4		T124	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T146	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T281	14		T36	12		T326	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T120	9		T43	8		T82	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T14	2		T15	6		T39	25
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T251	13		T126	16		T262	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T17	1		T168	1		T121	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T19	1		T120	9		T140	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T19	1		T155	11		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T42	6		T186	1		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T155	10		T118	10		T82	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T78	8		T255	3		T125	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T13	4		T29	1		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T129	1		T122	12		T247	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T168	2		T121	8		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T10	3		T151	1		T124	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T80	1		T124	2		T143	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T183	1		T197	1		T145	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T10	4		T11	2		T19	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T121	12		T151	16		T256	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1477	1			T16	1		T18	5		T20	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14016	1			T2	20		T3	20		T4	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T285	4		T359	2		T323	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T240	3		T127	8		T297	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T146	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T281	15		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T120	9		T43	3		T138	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T15	2		T39	10		T123	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T251	14		T126	14		T201	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T45	3		T125	3		T213	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T19	4		T120	8		T140	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T19	8		T44	1		T151	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T42	1		T186	5		T207	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T118	14		T82	9		T141	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T78	9		T125	8		T248	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T142	13		T169	8		T272	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T129	12		T247	1		T242	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T80	7		T283	12		T332	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T151	4		T124	13		T242	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T80	10		T146	7		T267	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T197	9		T145	7		T156	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T10	1		T19	14		T141	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T151	18		T171	3		T260	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1494	1			T20	25		T46	14		T164	15

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18746

1

T2

20

T3

20

T4

1

auto[1]

auto[0]

4222

1

T10

1

T15

2

T19

26