Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22968

1

T2

20

T3

20

T4

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19665

1

T2

20

T3

20

T4

1

auto[ADC_CTRL_FILTER_COND_OUT]

3303

1

T10

3

T14

2

T17

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16915

1

T2

20

T3

20

T4

1

auto[1]

6053

1

T10

5

T11

2

T14

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19141

1

T2

20

T3

20

T4

1

auto[1]

3827

1

T10

6

T11

1

T25

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	36	1			T55	6		T282	29		T360	1
values[0]	59	1			T19	5		T125	9		T292	20
values[1]	520	1			T10	5		T14	2		T120	17
values[2]	573	1			T155	10		T132	1		T80	8
values[3]	867	1			T186	6		T140	5		T124	2
values[4]	551	1			T19	15		T120	18		T168	2
values[5]	478	1			T173	3		T129	13		T80	14
values[6]	676	1			T10	3		T13	4		T15	8
values[7]	739	1			T16	1		T46	20		T43	11
values[8]	739	1			T183	1		T82	3		T151	26
values[9]	3714	1			T11	2		T17	1		T18	5
minimum	14016	1			T2	20		T3	20		T4	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	674	1			T10	5		T14	2		T19	5
values[1]	712	1			T155	10		T243	10		T151	5
values[2]	765	1			T19	15		T120	18		T186	6
values[3]	536	1			T168	1		T121	13		T129	13
values[4]	511	1			T10	3		T15	8		T173	3
values[5]	696	1			T16	1		T43	11		T236	27
values[6]	3195	1			T13	4		T18	5		T20	28
values[7]	735	1			T39	35		T183	1		T82	3
values[8]	865	1			T11	2		T17	1		T19	9
values[9]	220	1			T138	2		T141	16		T237	1
minimum	14059	1			T2	20		T3	20		T4	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18746

1

T2

20

T3

20

T4

1

auto[1]

4222

1

T10

1

T15

2

T19

26

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T10	3		T19	5		T138	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T14	1		T120	9		T121	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T155	1		T142	15		T143	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T243	1		T151	5		T143	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T19	15		T44	2		T123	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T120	10		T186	6		T168	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T168	1		T121	1		T129	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T262	1		T246	1		T157	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T15	6		T81	1		T258	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T10	2		T173	1		T168	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T16	1		T43	9		T152	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T236	15		T242	3		T252	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1762	1			T13	3		T18	1		T20	28
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T140	12		T80	11		T82	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T82	1		T247	2		T242	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T39	11		T183	1		T255	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T11	1		T42	6		T118	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T17	1		T19	9		T155	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T237	1		T126	12		T241	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T138	1		T141	16		T177	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13903	1			T2	20		T3	20		T4	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T310	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T10	2		T138	8		T125	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T14	1		T120	8		T121	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T155	9		T143	15		T156	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T243	9		T143	2		T127	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T44	1		T123	11		T124	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T120	8		T121	11		T213	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T121	12		T78	7		T244	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T262	10		T246	1		T267	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T15	2		T284	7		T271	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T10	1		T173	2		T138	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T43	2		T260	9		T55	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T236	12		T242	2		T252	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1018	1			T13	1		T18	4		T46	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T82	15		T151	10		T238	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T82	2		T247	1		T242	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T39	24		T152	6		T153	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T11	1		T42	1		T118	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T155	10		T247	1		T128	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T126	13		T176	15		T329	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T138	1		T282	13		T277	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T10	3		T25	2		T13	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T310	14		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T55	3		T360	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T282	17		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T19	5		T125	4		T348	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T292	12		T177	1		T331	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T10	3		T141	3		T144	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T14	1		T120	9		T121	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T155	1		T138	7		T142	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T132	1		T80	8		T82	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T124	1		T143	1		T281	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T186	6		T140	5		T281	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T19	15		T168	1		T44	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T120	10		T168	1		T121	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T129	13		T80	14		T81	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T173	1		T138	6		T29	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T13	3		T15	6		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T10	2		T168	1		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T16	1		T46	15		T43	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T140	12		T82	10		T236	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T82	1		T142	14		T242	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T183	1		T151	16		T255	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1805	1			T11	1		T18	1		T20	28
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	394	1			T17	1		T19	9		T39	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13898	1			T2	20		T3	20		T4	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T55	3		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T282	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T125	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T292	8		T331	9		T361	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T10	2		T171	9		T246	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T14	1		T120	8		T121	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T155	9		T138	8		T156	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T82	4		T243	9		T340	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T124	1		T143	15		T281	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T281	13		T262	10		T127	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T44	1		T121	12		T78	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T120	8		T121	11		T213	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T123	8		T284	7		T271	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T173	2		T138	4		T139	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T13	1		T15	2		T175	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T10	1		T238	11		T252	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T46	5		T43	2		T242	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T82	15		T236	12		T238	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T82	2		T242	2		T252	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T151	10		T153	10		T126	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1198	1			T11	1		T18	4		T42	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T39	24		T155	10		T138	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T10	3		T25	2		T13	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T10	4		T19	1		T138	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T14	2		T120	9		T121	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T155	10		T142	1		T143	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T243	10		T151	1		T143	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T19	1		T44	2		T123	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T120	9		T186	1		T168	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T168	1		T121	13		T129	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T262	11		T246	2		T157	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T15	6		T81	1		T258	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T10	3		T173	3		T168	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T16	1		T43	8		T152	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T236	13		T242	3		T252	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1376	1			T13	4		T18	5		T20	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T140	1		T80	1		T82	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T82	3		T247	2		T242	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T39	25		T183	1		T255	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T11	2		T42	6		T118	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T17	1		T19	1		T155	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T237	1		T126	14		T241	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T138	2		T141	1		T177	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14027	1			T2	20		T3	20		T4	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T310	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T10	1		T19	4		T138	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T120	8		T80	7		T240	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T142	14		T156	8		T248	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T151	4		T146	14		T127	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T19	14		T44	1		T123	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T120	9		T186	5		T140	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T129	12		T78	9		T80	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T267	4		T296	9		T277	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T15	2		T284	2		T159	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T138	5		T197	9		T169	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T43	3		T260	9		T55	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T236	14		T242	2		T252	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1404	1			T20	25		T46	14		T164	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T140	11		T80	10		T82	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T247	1		T242	8		T252	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T39	10		T153	10		T126	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T42	1		T118	14		T45	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T19	8		T201	13		T174	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T126	11		T329	10		T254	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T141	15		T282	11		T346	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T171	3		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T310	14		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T55	4		T360	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T282	13		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T19	1		T125	6		T348	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T292	9		T177	1		T331	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T10	4		T141	1		T144	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T14	2		T120	9		T121	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T155	10		T138	9		T142	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T132	1		T80	1		T82	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T124	2		T143	16		T281	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T186	1		T140	1		T281	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T19	1		T168	1		T44	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T120	9		T168	1		T121	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T129	1		T80	1		T81	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T173	3		T138	5		T29	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T13	4		T15	6		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T10	3		T168	1		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T16	1		T46	6		T43	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T140	1		T82	16		T236	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T82	3		T142	1		T242	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T183	1		T151	11		T255	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1581	1			T11	2		T18	5		T20	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	385	1			T17	1		T19	1		T39	25
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14016	1			T2	20		T3	20		T4	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T55	2		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T282	16		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T19	4		T125	3		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T292	11		T331	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T10	1		T141	2		T272	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T120	8		T240	3		T251	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T138	6		T142	14		T156	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T80	7		T151	4		T146	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T156	5		T207	8		T303	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T186	5		T140	4		T281	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T19	14		T44	1		T78	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T120	9		T174	12		T332	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T129	12		T80	13		T123	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T138	5		T197	9		T169	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T15	2		T197	21		T267	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T80	10		T252	11		T145	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T46	14		T43	3		T242	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T140	11		T82	9		T236	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T142	13		T242	6		T252	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T151	15		T153	10		T126	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1422	1			T20	25		T42	1		T164	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T19	8		T39	10		T141	15

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18746

1

T2

20

T3

20

T4

1

auto[1]

auto[0]

4222

1

T10

1

T15

2

T19

26