Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T265	5		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T158	1		T279	7		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T268	2		T271	1		T280	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T14	1		T155	1		T82	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T16	1		T155	1		T138	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T46	15		T43	9		T140	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T152	1		T169	13		T241	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T168	1		T243	1		T151	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T17	1		T39	11		T258	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T10	2		T42	6		T173	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T132	1		T171	5		T201	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1740	1			T18	1		T20	28		T37	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T11	1		T13	3		T19	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T120	10		T137	1		T82	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T281	16		T215	2		T275	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T82	1		T238	1		T169	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T15	6		T139	1		T236	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T168	1		T129	13		T141	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T120	9		T168	1		T29	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T10	3		T19	5		T186	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	339	1			T19	15		T121	1		T118	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13898	1			T2	20		T3	20		T4	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T268	3		T271	9		T280	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T14	1		T155	10		T82	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T155	9		T138	5		T122	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T46	5		T43	2		T153	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T152	6		T86	1		T176	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T243	9		T124	1		T238	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T39	24		T128	13		T263	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T10	1		T42	1		T173	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T171	5		T201	1		T260	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1086	1			T18	4		T165	21		T123	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T11	1		T13	1		T121	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T120	8		T82	4		T138	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T281	13		T275	6		T274	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T82	2		T238	11		T145	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T15	2		T139	12		T236	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T240	3		T125	12		T201	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T120	8		T247	1		T143	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T10	2		T121	11		T45	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T121	12		T118	9		T244	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T10	3		T25	2		T13	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T46	6		T43	8		T155	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T16	1		T155	10		T138	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T14	2		T140	1		T82	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T17	1		T142	1		T152	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T42	6		T173	3		T168	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T39	25		T258	1		T128	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1370	1			T10	3		T18	5		T20	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T121	8		T132	1		T144	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T123	21		T144	1		T128	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T11	2		T13	4		T19	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T120	9		T137	1		T82	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T139	13		T236	13		T157	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T129	1		T240	4		T238	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T15	6		T29	1		T247	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T168	1		T121	12		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T120	9		T168	1		T80	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T10	4		T19	1		T186	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T19	1		T121	13		T118	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T124	2		T272	1		T156	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T269	2		T273	3		T178	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14017	1			T2	20		T3	20		T4	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T46	14		T43	3		T197	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T138	5		T151	18		T169	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T140	11		T82	9		T252	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T142	14		T197	21		T263	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T42	1		T151	4		T142	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T39	10		T202	13		T282	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1360	1			T20	25		T164	15		T167	22
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T171	4		T201	11		T207	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T123	21		T283	9		T232	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T19	8		T281	15		T284	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T120	9		T138	6		T145	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T236	14		T274	13		T285	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T129	12		T240	3		T169	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T15	2		T247	1		T252	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T141	2		T125	11		T201	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T120	8		T80	13		T242	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T10	1		T19	4		T186	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T19	14		T118	14		T141	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T156	5		T216	6		T286	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T269	20		T273	2		T178	16

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T265	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T158	1		T279	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T268	4		T271	10		T280	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T14	2		T155	11		T82	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T16	1		T155	10		T138	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T46	6		T43	8		T140	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T152	7		T169	1		T241	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T168	1		T243	10		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T17	1		T39	25		T258	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T10	3		T42	6		T173	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T132	1		T171	6		T201	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1445	1			T18	5		T20	3		T37	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T11	2		T13	4		T19	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T120	9		T137	1		T82	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T281	14		T215	2		T275	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T82	3		T238	12		T169	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T15	6		T139	13		T236	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T168	1		T129	1		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T120	9		T168	1		T29	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	334	1			T10	4		T19	1		T186	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T19	1		T121	13		T118	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14016	1			T2	20		T3	20		T4	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T265	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T279	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T268	1		T280	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T82	9		T197	9		T242	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T138	5		T151	18		T142	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T46	14		T43	3		T140	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T169	12		T249	13		T187	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T151	4		T142	13		T169	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T39	10		T263	12		T202	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T42	1		T44	1		T251	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T171	4		T201	11		T260	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1381	1			T20	25		T164	15		T167	22
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T19	8		T207	11		T284	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T120	9		T138	6		T123	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T281	15		T274	13		T282	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T169	8		T145	6		T283	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T15	2		T236	14		T252	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T129	12		T141	2		T240	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T120	8		T247	1		T145	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T10	1		T19	4		T186	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T19	14		T118	14		T80	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18746

1

T2

20

T3

20

T4

1

auto[1]

auto[0]

4222

1

T10

1

T15

2

T19

26