Summary for Variable clk_gate_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for clk_gate_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 22968 1 T2 20 T3 20 T4 1


Summary for Variable cond_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cond_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[ADC_CTRL_FILTER_COND_IN] 19607 1 T2 20 T3 20 T4 1
auto[ADC_CTRL_FILTER_COND_OUT] 3361 1 T10 8 T11 2 T13 4


Summary for Variable en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for en_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 16995 1 T2 20 T3 20 T4 1
auto[1] 5973 1 T11 2 T15 8 T16 1


Summary for Variable interrupt_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for interrupt_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 19141 1 T2 20 T3 20 T4 1
auto[1] 3827 1 T10 6 T11 1 T25 2


Summary for Variable max_v_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 12 0 12 100.00


User Defined Bins for max_v_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
maximum 30 1 T301 30 - - - -
values[0] 49 1 T155 10 T188 1 T181 10
values[1] 564 1 T10 5 T13 4 T16 1
values[2] 3198 1 T18 5 T20 28 T37 1
values[3] 599 1 T168 1 T137 1 T140 12
values[4] 790 1 T42 7 T173 3 T183 1
values[5] 695 1 T19 14 T46 20 T120 18
values[6] 664 1 T19 15 T44 3 T80 14
values[7] 524 1 T11 2 T17 1 T120 17
values[8] 690 1 T14 2 T15 8 T121 8
values[9] 1149 1 T10 3 T155 11 T140 5
minimum 14016 1 T2 20 T3 20 T4 1


Summary for Variable min_v_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 12 1 11 91.67


User Defined Bins for min_v_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
maximum 0 1 1


Covered bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
values[0] 802 1 T10 5 T13 4 T16 1
values[1] 3048 1 T18 5 T20 28 T37 1
values[2] 669 1 T39 35 T168 1 T137 1
values[3] 805 1 T42 7 T173 3 T168 2
values[4] 776 1 T19 29 T46 20 T120 18
values[5] 591 1 T11 2 T120 17 T80 25
values[6] 708 1 T15 8 T17 1 T43 11
values[7] 586 1 T14 2 T121 8 T129 13
values[8] 754 1 T10 3 T155 11 T152 7
values[9] 191 1 T140 5 T236 27 T171 10
minimum 14038 1 T2 20 T3 20 T4 1


Summary for Variable wakeup_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wakeup_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 18746 1 T2 20 T3 20 T4 1
auto[1] 4222 1 T10 1 T15 2 T19 26


Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 6 42 87.50 6


Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes
interrupt_cp   min_v_cp   cond_cp   COUNT   AT LEAST   NUMBER   STATUS   
* [maximum] * -- -- 4
* [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] -- -- 2


Covered bins
interrupt_cp   min_v_cp   cond_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 189 1 T81 1 T82 1 T240 4
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 277 1 T10 3 T13 3 T16 1
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 1716 1 T18 1 T20 28 T37 1
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 155 1 T45 8 T122 1 T238 1
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 174 1 T140 12 T123 10 T139 1
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 205 1 T39 11 T168 1 T137 1
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 202 1 T42 6 T168 1 T183 1
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 231 1 T173 1 T168 1 T124 14
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 230 1 T19 14 T46 15 T78 10
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 266 1 T19 15 T120 10 T44 2
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 187 1 T120 9 T80 25 T82 10
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 107 1 T11 1 T255 3 T144 1
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 155 1 T17 1 T132 1 T141 3
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 230 1 T15 6 T43 9 T121 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 162 1 T14 1 T121 1 T80 8
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 176 1 T129 13 T151 5 T124 1
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 187 1 T152 1 T256 1 T252 19
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 260 1 T10 2 T155 1 T213 8
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 96 1 T140 5 T171 5 T302 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 26 1 T236 15 T271 1 T303 8
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 13910 1 T2 20 T3 20 T4 1
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_IN] 95 1 T82 2 T240 3 T153 10
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 241 1 T10 2 T13 1 T155 9
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 1035 1 T18 4 T165 21 T304 25
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 142 1 T45 3 T122 11 T238 11
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 138 1 T123 11 T139 12 T145 8
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 152 1 T39 24 T151 15 T124 1
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 177 1 T42 1 T121 11 T82 4
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 195 1 T173 2 T124 14 T145 9
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 181 1 T46 5 T78 7 T138 4
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 99 1 T120 8 T44 1 T246 1
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 173 1 T120 8 T82 15 T138 8
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 124 1 T11 1 T128 13 T305 9
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 136 1 T247 1 T143 15 T257 2
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 187 1 T15 2 T43 2 T121 12
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 138 1 T14 1 T121 7 T151 10
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 110 1 T124 1 T247 1 T232 3
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 153 1 T152 6 T252 20 T171 6
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 154 1 T10 1 T155 10 T213 1
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 45 1 T171 5 T306 1 T298 10
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 24 1 T236 12 T271 12 - -
auto[1] minimum auto[ADC_CTRL_FILTER_COND_IN] 128 1 T10 3 T25 2 T13 1


Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 5 43 89.58 5


Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins
interrupt_cp   max_v_cp   cond_cp   COUNT   AT LEAST   NUMBER   STATUS   
[auto[0]] [maximum] [auto[ADC_CTRL_FILTER_COND_IN]] 0 1 1
[auto[0]] [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] 0 1 1
[auto[1]] [maximum , values[0]] [auto[ADC_CTRL_FILTER_COND_IN]] -- -- 2
[auto[1]] [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] 0 1 1


Covered bins
interrupt_cp   max_v_cp   cond_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] maximum auto[ADC_CTRL_FILTER_COND_OUT] 15 1 T301 15 - - - -
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 2 1 T188 1 T307 1 - -
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 18 1 T155 1 T181 1 T308 16
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 127 1 T81 1 T82 1 T153 11
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 182 1 T10 3 T13 3 T16 1
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 1757 1 T18 1 T20 28 T37 1
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 234 1 T39 11 T45 8 T238 1
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 183 1 T140 12 T123 10 T241 1
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 136 1 T168 1 T137 1 T151 19
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 156 1 T42 6 T183 1 T121 1
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 299 1 T173 1 T124 14 T142 29
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 205 1 T19 14 T46 15 T168 1
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 203 1 T120 10 T168 1 T146 15
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 218 1 T80 14 T82 10 T138 7
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 139 1 T19 15 T44 2 T255 3
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 146 1 T17 1 T120 9 T132 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 148 1 T11 1 T43 9 T121 1
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 197 1 T14 1 T121 1 T80 8
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 204 1 T15 6 T129 13 T118 15
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 319 1 T140 5 T152 1 T256 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 355 1 T10 2 T155 1 T236 15
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 13898 1 T2 20 T3 20 T4 1
auto[1] maximum auto[ADC_CTRL_FILTER_COND_OUT] 15 1 T301 15 - - - -
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 29 1 T155 9 T181 9 T308 11
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 96 1 T82 2 T153 10 T242 8
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 159 1 T10 2 T13 1 T243 9
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 1019 1 T18 4 T165 21 T304 25
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 188 1 T39 24 T45 3 T238 11
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 145 1 T123 11 T145 8 T156 2
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 135 1 T151 15 T124 1 T274 1
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 123 1 T42 1 T121 11 T82 4
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 212 1 T173 2 T124 14 T145 9
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 175 1 T46 5 T78 7 T123 8
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 112 1 T120 8 T246 1 T174 8
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 210 1 T82 15 T138 8 T242 2
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 97 1 T44 1 T128 13 T305 9
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 113 1 T120 8 T247 1 T143 15
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 117 1 T11 1 T43 2 T121 12
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 147 1 T14 1 T121 7 T151 10
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 142 1 T15 2 T118 9 T125 7
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 253 1 T152 6 T143 2 T252 20
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 222 1 T10 1 T155 10 T236 12
auto[1] minimum auto[ADC_CTRL_FILTER_COND_IN] 118 1 T10 3 T25 2 T13 1


Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 6 42 87.50 6


Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes
wakeup_cp   min_v_cp   cond_cp   COUNT   AT LEAST   NUMBER   STATUS   
* [maximum] * -- -- 4
* [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] -- -- 2


Covered bins
wakeup_cp   min_v_cp   cond_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 132 1 T81 1 T82 3 T240 4
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 299 1 T10 4 T13 4 T16 1
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 1393 1 T18 5 T20 3 T37 1
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 178 1 T45 8 T122 12 T238 12
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 166 1 T140 1 T123 12 T139 13
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 198 1 T39 25 T168 1 T137 1
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 220 1 T42 6 T168 1 T183 1
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 229 1 T173 3 T168 1 T124 15
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 225 1 T19 2 T46 6 T78 8
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 134 1 T19 1 T120 9 T44 2
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 206 1 T120 9 T80 2 T82 16
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 156 1 T11 2 T255 3 T144 1
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 168 1 T17 1 T132 1 T141 1
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 230 1 T15 6 T43 8 T121 13
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 165 1 T14 2 T121 8 T80 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 142 1 T129 1 T151 1 T124 2
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 184 1 T152 7 T256 1 T252 21
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 204 1 T10 3 T155 11 T213 3
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 61 1 T140 1 T171 6 T302 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 29 1 T236 13 T271 13 T303 1
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 14027 1 T2 20 T3 20 T4 1
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_IN] 152 1 T240 3 T153 10 T242 8
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 219 1 T10 1 T252 11 T283 12
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 1358 1 T20 25 T186 5 T164 15
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 119 1 T45 3 T274 1 T266 1
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 146 1 T140 11 T123 9 T197 21
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 159 1 T39 10 T151 18 T142 13
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 159 1 T42 1 T197 9 T242 6
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 197 1 T124 13 T142 14 T145 7
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 186 1 T19 12 T46 14 T78 9
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 231 1 T19 14 T120 9 T44 1
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 154 1 T120 8 T80 23 T82 9
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 75 1 T305 9 T266 9 T282 16
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 123 1 T141 2 T247 1 T300 9
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 187 1 T15 2 T43 3 T118 14
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 135 1 T80 7 T151 15 T251 14
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 144 1 T129 12 T151 4 T272 15
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 156 1 T252 18 T171 4 T309 8
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 210 1 T213 6 T281 15 T268 1
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 80 1 T140 4 T171 4 T306 6
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 21 1 T236 14 T303 7 - -
auto[1] minimum auto[ADC_CTRL_FILTER_COND_IN] 11 1 T282 11 - - - -


Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 6 42 87.50 6


Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes
wakeup_cpmax_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [minimum] * -- -- 2


Uncovered bins
wakeup_cp   max_v_cp   cond_cp   COUNT   AT LEAST   NUMBER   STATUS   
[auto[0]] [maximum] [auto[ADC_CTRL_FILTER_COND_IN]] 0 1 1
[auto[0]] [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] 0 1 1
[auto[1]] [maximum , values[0]] [auto[ADC_CTRL_FILTER_COND_IN]] -- -- 2


Covered bins
wakeup_cp   max_v_cp   cond_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] maximum auto[ADC_CTRL_FILTER_COND_OUT] 16 1 T301 16 - - - -
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 2 1 T188 1 T307 1 - -
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 32 1 T155 10 T181 10 T308 12
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 122 1 T81 1 T82 3 T153 11
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 203 1 T10 4 T13 4 T16 1
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 1380 1 T18 5 T20 3 T37 1
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 231 1 T39 25 T45 8 T238 12
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 176 1 T140 1 T123 12 T241 1
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 172 1 T168 1 T137 1 T151 16
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 159 1 T42 6 T183 1 T121 12
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 254 1 T173 3 T124 15 T142 2
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 210 1 T19 2 T46 6 T168 1
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 143 1 T120 9 T168 1 T146 1
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 253 1 T80 1 T82 16 T138 9
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 131 1 T19 1 T44 2 T255 3
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 142 1 T17 1 T120 9 T132 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 148 1 T11 2 T43 8 T121 13
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 178 1 T14 2 T121 8 T80 1
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 182 1 T15 6 T129 1 T118 10
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 309 1 T140 1 T152 7 T256 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 287 1 T10 3 T155 11 T236 13
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 14016 1 T2 20 T3 20 T4 1
auto[1] maximum auto[ADC_CTRL_FILTER_COND_OUT] 14 1 T301 14 - - - -
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 15 1 T308 15 - - - -
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 101 1 T153 10 T242 8 T201 24
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 138 1 T10 1 T283 12 T156 5
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 1396 1 T20 25 T186 5 T164 15
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 191 1 T39 10 T45 3 T252 11
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 152 1 T140 11 T123 9 T145 6
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 99 1 T151 18 T274 1 T273 2
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 120 1 T42 1 T138 5 T126 11
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 257 1 T124 13 T142 27 T145 7
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 170 1 T19 12 T46 14 T78 9
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 172 1 T120 9 T146 14 T174 12
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 175 1 T80 13 T82 9 T138 6
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 105 1 T19 14 T44 1 T207 8
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 117 1 T120 8 T80 10 T247 1
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 117 1 T43 3 T125 3 T126 14
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 166 1 T80 7 T141 2 T151 15
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 164 1 T15 2 T129 12 T118 14
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 263 1 T140 4 T252 18 T171 11
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 290 1 T236 14 T272 15 T213 6


Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 2 2 50.00 2


Automatically Generated Cross Bins for wakeup_gated_xp

Element holes
wakeup_cpclk_gate_cpCOUNTAT LEASTNUMBERSTATUS
* [auto[1]] -- -- 2


Covered bins
wakeup_cp   clk_gate_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] auto[0] 18746 1 T2 20 T3 20 T4 1
auto[1] auto[0] 4222 1 T10 1 T15 2 T19 26