Summary for Variable clk_gate_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for clk_gate_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 22968 1 T2 20 T3 20 T4 1


Summary for Variable cond_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cond_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[ADC_CTRL_FILTER_COND_IN] 17052 1 T2 20 T3 20 T4 1
auto[ADC_CTRL_FILTER_COND_OUT] 5916 1 T10 5 T11 2 T13 4


Summary for Variable en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for en_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 17357 1 T2 20 T3 20 T4 1
auto[1] 5611 1 T10 5 T13 4 T17 1


Summary for Variable interrupt_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for interrupt_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 19141 1 T2 20 T3 20 T4 1
auto[1] 3827 1 T10 6 T11 1 T25 2


Summary for Variable max_v_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 12 0 12 100.00


User Defined Bins for max_v_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
maximum 11 1 T245 1 T320 10 - -
values[0] 59 1 T281 29 T36 12 T321 3
values[1] 697 1 T14 2 T15 8 T39 35
values[2] 749 1 T17 1 T168 1 T121 13
values[3] 571 1 T19 14 T120 17 T155 11
values[4] 849 1 T42 7 T186 6 T155 10
values[5] 679 1 T13 4 T29 1 T255 3
values[6] 647 1 T168 2 T121 8 T129 13
values[7] 630 1 T10 3 T183 1 T151 5
values[8] 513 1 T10 5 T11 2 T80 11
values[9] 3547 1 T16 1 T18 5 T19 15
minimum 14016 1 T2 20 T3 20 T4 1


Summary for Variable min_v_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 12 1 11 91.67


User Defined Bins for min_v_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
maximum 0 1 1


Covered bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
values[0] 958 1 T14 2 T15 8 T39 35
values[1] 3109 1 T17 1 T18 5 T20 28
values[2] 652 1 T19 14 T137 1 T44 3
values[3] 765 1 T42 7 T186 6 T155 21
values[4] 835 1 T13 4 T168 1 T121 8
values[5] 547 1 T10 3 T168 1 T129 13
values[6] 567 1 T183 1 T80 11 T151 5
values[7] 585 1 T10 5 T11 2 T19 15
values[8] 723 1 T16 1 T46 20 T121 12
values[9] 185 1 T173 3 T124 2 T256 1
minimum 14042 1 T2 20 T3 20 T4 1


Summary for Variable wakeup_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wakeup_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 18746 1 T2 20 T3 20 T4 1
auto[1] 4222 1 T10 1 T15 2 T19 26


Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 5 43 89.58 5


Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes
interrupt_cp   min_v_cp   cond_cp   COUNT   AT LEAST   NUMBER   STATUS   
[auto[0]] [maximum] * -- -- 2
[auto[1]] [maximum] * -- -- 2


Uncovered bins
interrupt_cpmin_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] 0 1 1


Covered bins
interrupt_cp   min_v_cp   cond_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 242 1 T120 10 T43 9 T82 1
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 263 1 T14 1 T15 6 T39 11
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 210 1 T120 9 T126 15 T262 1
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 1734 1 T17 1 T18 1 T20 28
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 155 1 T19 5 T140 17 T236 15
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 200 1 T19 9 T137 1 T44 2
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 211 1 T42 6 T186 6 T137 1
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 228 1 T155 2 T82 10 T141 16
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 198 1 T121 1 T78 10 T122 1
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 272 1 T13 3 T168 1 T139 1
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 167 1 T10 2 T129 13 T124 14
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 133 1 T168 1 T132 1 T80 8
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 128 1 T183 1 T151 5 T237 1
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 189 1 T80 11 T124 1 T143 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 187 1 T151 19 T197 10 T145 8
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 180 1 T10 3 T11 1 T19 15
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 151 1 T121 1 T245 1 T171 4
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 271 1 T16 1 T46 15 T80 14
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 40 1 T256 1 T246 1 T268 2
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 67 1 T173 1 T124 1 T76 1
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 13913 1 T2 20 T3 20 T4 1
auto[0] minimum auto[ADC_CTRL_FILTER_COND_OUT] 2 1 T322 1 T323 1 - -
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_IN] 205 1 T120 8 T43 2 T82 4
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 248 1 T14 1 T15 2 T39 24
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 124 1 T120 8 T126 15 T262 10
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 1041 1 T18 4 T165 21 T45 3
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 133 1 T236 12 T213 1 T171 5
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 164 1 T44 1 T121 12 T118 9
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 128 1 T42 1 T239 1 T261 2
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 198 1 T155 19 T82 15 T175 6
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 184 1 T121 7 T78 7 T122 11
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 181 1 T13 1 T139 12 T152 6
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 125 1 T10 1 T124 14 T247 2
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 122 1 T267 2 T305 9 T176 15
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 108 1 T171 6 T156 2 T324 25
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 142 1 T124 1 T143 2 T242 2
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 121 1 T151 15 T145 9 T213 1
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 97 1 T10 2 T11 1 T153 10
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 151 1 T121 11 T171 9 T214 6
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 150 1 T46 5 T244 11 T240 3
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 44 1 T246 1 T268 3 T216 14
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 34 1 T173 2 T124 1 T127 10
auto[1] minimum auto[ADC_CTRL_FILTER_COND_IN] 127 1 T10 3 T25 2 T13 1


Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 4 44 91.67 4


Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes
interrupt_cpmax_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [maximum] * -- -- 2


Uncovered bins
interrupt_cp   max_v_cp   cond_cp   COUNT   AT LEAST   NUMBER   STATUS   
[auto[0]] [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] 0 1 1
[auto[1]] [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] 0 1 1


Covered bins
interrupt_cp   max_v_cp   cond_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] maximum auto[ADC_CTRL_FILTER_COND_IN] 1 1 T245 1 - - - -
auto[0] maximum auto[ADC_CTRL_FILTER_COND_OUT] 10 1 T320 10 - - - -
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 1 1 T325 1 - - - -
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 21 1 T281 16 T36 1 T321 3
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 184 1 T120 10 T43 9 T82 1
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 175 1 T14 1 T15 6 T39 11
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 215 1 T251 15 T126 15 T262 1
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 240 1 T17 1 T168 1 T121 1
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 166 1 T19 5 T120 9 T140 17
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 152 1 T19 9 T155 1 T137 1
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 235 1 T42 6 T186 6 T137 1
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 241 1 T155 1 T118 15 T82 10
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 138 1 T29 1 T255 3 T125 9
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 259 1 T13 3 T142 14 T169 9
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 206 1 T121 1 T129 13 T122 1
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 151 1 T168 2 T132 1 T80 8
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 170 1 T10 2 T183 1 T151 5
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 171 1 T124 1 T143 1 T144 1
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 117 1 T197 10 T258 1 T156 9
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 200 1 T10 3 T11 1 T80 11
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 271 1 T121 1 T151 19 T256 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 1919 1 T16 1 T18 1 T19 15
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 13898 1 T2 20 T3 20 T4 1
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_IN] 12 1 T325 12 - - - -
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 25 1 T281 13 T36 11 T326 1
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 161 1 T120 8 T43 2 T82 4
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 177 1 T14 1 T15 2 T39 24
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 123 1 T251 12 T126 15 T262 10
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 171 1 T121 12 T45 3 T82 2
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 126 1 T120 8 T236 12 T213 1
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 127 1 T155 10 T44 1 T151 10
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 168 1 T42 1 T78 7 T239 1
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 205 1 T155 9 T118 9 T82 15
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 127 1 T125 7 T143 15 T261 2
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 155 1 T13 1 T174 8 T275 15
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 158 1 T121 7 T122 11 T247 2
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 132 1 T139 12 T152 6 T267 18
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 134 1 T10 1 T124 14 T252 10
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 155 1 T124 1 T143 2 T242 2
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 84 1 T156 2 T158 2 T295 4
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 112 1 T10 2 T11 1 T153 10
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 239 1 T121 11 T151 15 T213 1
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 1118 1 T18 4 T173 2 T46 5
auto[1] minimum auto[ADC_CTRL_FILTER_COND_IN] 118 1 T10 3 T25 2 T13 1


Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 5 43 89.58 5


Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes
wakeup_cp   min_v_cp   cond_cp   COUNT   AT LEAST   NUMBER   STATUS   
[auto[0]] [maximum] * -- -- 2
[auto[1]] [maximum] * -- -- 2


Uncovered bins
wakeup_cpmin_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] 0 1 1


Covered bins
wakeup_cp   min_v_cp   cond_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 255 1 T120 9 T43 8 T82 5
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 298 1 T14 2 T15 6 T39 25
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 155 1 T120 9 T126 16 T262 11
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 1401 1 T17 1 T18 5 T20 3
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 162 1 T19 1 T140 2 T236 13
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 210 1 T19 1 T137 1 T44 2
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 168 1 T42 6 T186 1 T137 1
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 230 1 T155 21 T82 16 T141 1
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 227 1 T121 8 T78 8 T122 12
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 221 1 T13 4 T168 1 T139 13
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 163 1 T10 3 T129 1 T124 15
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 146 1 T168 1 T132 1 T80 1
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 141 1 T183 1 T151 1 T237 1
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 178 1 T80 1 T124 2 T143 3
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 153 1 T151 16 T197 1 T145 10
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 129 1 T10 4 T11 2 T19 1
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 186 1 T121 12 T245 1 T171 10
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 191 1 T16 1 T46 6 T80 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 55 1 T256 1 T246 2 T268 4
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 46 1 T173 3 T124 2 T76 1
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 14029 1 T2 20 T3 20 T4 1
auto[0] minimum auto[ADC_CTRL_FILTER_COND_OUT] 2 1 T322 1 T323 1 - -
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_IN] 192 1 T120 9 T43 3 T138 11
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 213 1 T15 2 T39 10 T169 12
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 179 1 T120 8 T126 14 T201 13
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 1374 1 T20 25 T164 15 T167 22
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 126 1 T19 4 T140 15 T236 14
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 154 1 T19 8 T44 1 T118 14
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 171 1 T42 1 T186 5 T207 8
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 196 1 T82 9 T141 15 T197 21
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 155 1 T78 9 T125 8 T242 2
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 232 1 T142 13 T272 15 T145 6
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 129 1 T129 12 T124 13 T247 1
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 109 1 T80 7 T267 7 T305 9
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 95 1 T151 4 T171 4 T156 8
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 153 1 T80 10 T242 6 T146 7
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 155 1 T151 18 T197 9 T145 7
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 148 1 T10 1 T19 14 T141 2
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 116 1 T171 3 T232 11 T265 4
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 230 1 T46 14 T80 13 T240 3
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 29 1 T268 1 T216 13 T294 4
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 55 1 T127 8 T216 6 T296 9
auto[1] minimum auto[ADC_CTRL_FILTER_COND_IN] 11 1 T305 10 T327 1 - -


Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 5 43 89.58 5


Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes
wakeup_cpmax_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [minimum] * -- -- 2


Uncovered bins
wakeup_cp   max_v_cp   cond_cp   COUNT   AT LEAST   NUMBER   STATUS   
[auto[0]] [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] 0 1 1
[auto[1]] [maximum , values[0]] [auto[ADC_CTRL_FILTER_COND_IN]] -- -- 2


Covered bins
wakeup_cp   max_v_cp   cond_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] maximum auto[ADC_CTRL_FILTER_COND_IN] 1 1 T245 1 - - - -
auto[0] maximum auto[ADC_CTRL_FILTER_COND_OUT] 1 1 T320 1 - - - -
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 13 1 T325 13 - - - -
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 31 1 T281 14 T36 12 T321 3
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 207 1 T120 9 T43 8 T82 5
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 215 1 T14 2 T15 6 T39 25
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 151 1 T251 13 T126 16 T262 11
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 216 1 T17 1 T168 1 T121 13
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 156 1 T19 1 T120 9 T140 2
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 159 1 T19 1 T155 11 T137 1
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 210 1 T42 6 T186 1 T137 1
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 249 1 T155 10 T118 10 T82 16
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 163 1 T29 1 T255 3 T125 8
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 188 1 T13 4 T142 1 T169 1
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 203 1 T121 8 T129 1 T122 12
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 163 1 T168 2 T132 1 T80 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 169 1 T10 3 T183 1 T151 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 185 1 T124 2 T143 3 T144 1
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 111 1 T197 1 T258 1 T156 3
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 146 1 T10 4 T11 2 T80 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 294 1 T121 12 T151 16 T256 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 1499 1 T16 1 T18 5 T19 1
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 14016 1 T2 20 T3 20 T4 1
auto[1] maximum auto[ADC_CTRL_FILTER_COND_OUT] 9 1 T320 9 - - - -
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 15 1 T281 15 - - - -
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 138 1 T120 9 T43 3 T138 11
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 137 1 T15 2 T39 10 T169 12
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 187 1 T251 14 T126 14 T201 13
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 195 1 T45 3 T125 3 T213 6
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 136 1 T19 4 T120 8 T140 15
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 120 1 T19 8 T44 1 T151 15
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 193 1 T42 1 T186 5 T78 9
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 197 1 T118 14 T82 9 T141 15
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 102 1 T125 8 T207 8 T248 11
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 226 1 T142 13 T169 8 T272 15
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 161 1 T129 12 T247 1 T242 2
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 120 1 T80 7 T283 12 T267 4
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 135 1 T151 4 T124 13 T252 11
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 141 1 T242 6 T146 7 T267 7
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 90 1 T197 9 T156 8 T158 10
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 166 1 T10 1 T80 10 T141 2
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 216 1 T151 18 T171 3 T260 9
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 1538 1 T19 14 T20 25 T46 14


Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 2 2 50.00 2


Automatically Generated Cross Bins for wakeup_gated_xp

Element holes
wakeup_cpclk_gate_cpCOUNTAT LEASTNUMBERSTATUS
* [auto[1]] -- -- 2


Covered bins
wakeup_cp   clk_gate_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] auto[0] 18746 1 T2 20 T3 20 T4 1
auto[1] auto[0] 4222 1 T10 1 T15 2 T19 26