AES/MASKED Simulation Results

Wednesday May 17 2023 07:05:42 UTC

GitHub Revision: `3df77bec1`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 2320738200

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	2.000s	98.951us	1	1	100.00
V1	smoke	aes_smoke	15.000s	755.045us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	50.449us	5	5	100.00
V1	csr_rw	aes_csr_rw	4.000s	168.629us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	11.000s	858.588us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	254.376us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	5.000s	179.009us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	168.629us	20	20	100.00
		aes_csr_aliasing	5.000s	254.376us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	15.000s	755.045us	50	50	100.00
		aes_config_error	13.000s	374.265us	50	50	100.00
		aes_stress	2.067m	4.951ms	50	50	100.00
V2	key_length	aes_smoke	15.000s	755.045us	50	50	100.00
		aes_config_error	13.000s	374.265us	50	50	100.00
		aes_stress	2.067m	4.951ms	50	50	100.00
V2	back2back	aes_stress	2.067m	4.951ms	50	50	100.00
		aes_b2b	1.267m	973.996us	50	50	100.00
V2	backpressure	aes_stress	2.067m	4.951ms	50	50	100.00
V2	multi_message	aes_smoke	15.000s	755.045us	50	50	100.00
		aes_config_error	13.000s	374.265us	50	50	100.00
		aes_stress	2.067m	4.951ms	50	50	100.00
		aes_alert_reset	9.000s	991.232us	50	50	100.00
V2	failure_test	aes_config_error	13.000s	374.265us	50	50	100.00
		aes_alert_reset	9.000s	991.232us	50	50	100.00
		aes_man_cfg_err	11.000s	438.158us	50	50	100.00
V2	trigger_clear_test	aes_clear	24.000s	1.453ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	17.000s	2.316ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	9.000s	991.232us	50	50	100.00
V2	stress	aes_stress	2.067m	4.951ms	50	50	100.00
V2	sideload	aes_stress	2.067m	4.951ms	50	50	100.00
		aes_sideload	42.000s	1.491ms	50	50	100.00
V2	deinitialization	aes_deinit	2.183m	4.269ms	50	50	100.00
V2	alert_test	aes_alert_test	5.000s	54.780us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	7.000s	166.251us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	7.000s	166.251us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	50.449us	5	5	100.00
		aes_csr_rw	4.000s	168.629us	20	20	100.00
		aes_csr_aliasing	5.000s	254.376us	5	5	100.00
		aes_same_csr_outstanding	5.000s	160.570us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	50.449us	5	5	100.00
		aes_csr_rw	4.000s	168.629us	20	20	100.00
		aes_csr_aliasing	5.000s	254.376us	5	5	100.00
		aes_same_csr_outstanding	5.000s	160.570us	20	20	100.00
V2		TOTAL			491	491	100.00
V2S	reseeding	aes_reseed	3.250m	2.128ms	50	50	100.00
V2S	fault_inject	aes_fi	51.000s	1.764ms	50	50	100.00
		aes_control_fi	43.000s	10.006ms	281	300	93.67
		aes_cipher_fi	51.000s	10.009ms	338	350	96.57
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	124.940us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	124.940us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	124.940us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	124.940us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	6.000s	632.102us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	7.000s	813.562us	5	5	100.00
		aes_tl_intg_err	6.000s	755.801us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	755.801us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	9.000s	991.232us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	124.940us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	15.000s	755.045us	50	50	100.00
		aes_stress	2.067m	4.951ms	50	50	100.00
		aes_alert_reset	9.000s	991.232us	50	50	100.00
		aes_core_fi	1.417m	10.011ms	68	70	97.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	124.940us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_stress	2.067m	4.951ms	50	50	100.00
		aes_readability	7.000s	233.536us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	2.067m	4.951ms	50	50	100.00
		aes_sideload	42.000s	1.491ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	7.000s	233.536us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	7.000s	233.536us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	7.000s	233.536us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	7.000s	233.536us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	7.000s	233.536us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	2.067m	4.951ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	2.067m	4.951ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	51.000s	1.764ms	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	51.000s	1.764ms	50	50	100.00
		aes_control_fi	43.000s	10.006ms	281	300	93.67
		aes_cipher_fi	51.000s	10.009ms	338	350	96.57
		aes_ctr_fi	6.000s	299.997us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	51.000s	1.764ms	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	51.000s	1.764ms	50	50	100.00
		aes_control_fi	43.000s	10.006ms	281	300	93.67
		aes_cipher_fi	51.000s	10.009ms	338	350	96.57
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	51.000s	10.009ms	338	350	96.57
V2S	sec_cm_ctr_fsm_sparse	aes_fi	51.000s	1.764ms	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	51.000s	1.764ms	50	50	100.00
		aes_control_fi	43.000s	10.006ms	281	300	93.67
		aes_ctr_fi	6.000s	299.997us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	51.000s	1.764ms	50	50	100.00
		aes_control_fi	43.000s	10.006ms	281	300	93.67
		aes_cipher_fi	51.000s	10.009ms	338	350	96.57
		aes_ctr_fi	6.000s	299.997us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	9.000s	991.232us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	51.000s	1.764ms	50	50	100.00
		aes_control_fi	43.000s	10.006ms	281	300	93.67
		aes_cipher_fi	51.000s	10.009ms	338	350	96.57
		aes_ctr_fi	6.000s	299.997us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	51.000s	1.764ms	50	50	100.00
		aes_control_fi	43.000s	10.006ms	281	300	93.67
		aes_cipher_fi	51.000s	10.009ms	338	350	96.57
		aes_ctr_fi	6.000s	299.997us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	51.000s	1.764ms	50	50	100.00
		aes_control_fi	43.000s	10.006ms	281	300	93.67
		aes_ctr_fi	6.000s	299.997us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	51.000s	1.764ms	50	50	100.00
		aes_control_fi	43.000s	10.006ms	281	300	93.67
		aes_cipher_fi	51.000s	10.009ms	338	350	96.57
V2S		TOTAL			952	985	96.65
V3		TOTAL			0	0	--
		TOTAL			1549	1582	97.91

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	12	12	12	100.00
V2S	11	11	8	72.73

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.47	99.01	97.53	99.42	95.83	95.66	98.52	98.67	92.49

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 18 failures:
- Test aes_control_fi has 14 failures.
  - 20.aes_control_fi.2340956895
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/20.aes_control_fi/latest/run.log
```
  Job ID: smart:9487f826-8be4-48c5-8f45-d65e7ec82cda
```
  - 26.aes_control_fi.1453176476
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/26.aes_control_fi/latest/run.log
```
  Job ID: smart:687b468c-7aa1-4e5e-8c73-498f96125c82
```
  - ... and 12 more failures.
- Test aes_cipher_fi has 4 failures.
  - 68.aes_cipher_fi.1298253243
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/68.aes_cipher_fi/latest/run.log
```
  Job ID: smart:d645b5e1-29f9-422a-a583-6566df982815
```
  - 212.aes_cipher_fi.36673004
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/212.aes_cipher_fi/latest/run.log
```
  Job ID: smart:6277dc6b-3fe1-4d75-bae8-cdcb8cd06710
```
  - ... and 2 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 8 failures:

Test aes_cipher_fi has 8 failures.

1.aes_cipher_fi.3319496515
Line 279, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_cipher_fi/latest/run.log

  UVM_FATAL @ 10004987045 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004987045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_cipher_fi.1997140326
Line 282, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_cipher_fi/latest/run.log

  UVM_FATAL @ 10035618025 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10035618025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 5 failures:

Test aes_control_fi has 5 failures.

77.aes_control_fi.3640618786
Line 282, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/77.aes_control_fi/latest/run.log

  UVM_FATAL @ 10005731491 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005731491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

148.aes_control_fi.2714342473
Line 286, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/148.aes_control_fi/latest/run.log

  UVM_FATAL @ 10020241528 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10020241528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:

Test aes_core_fi has 2 failures.

52.aes_core_fi.337066559
Line 284, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/52.aes_core_fi/latest/run.log

  UVM_FATAL @ 10005392061 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005392061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

55.aes_core_fi.3231777325
Line 274, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/55.aes_core_fi/latest/run.log

  UVM_FATAL @ 10010924349 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010924349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---