AES/MASKED Simulation Results

Tuesday April 23 2024 19:02:21 UTC

GitHub Revision: `41bc3e0c7f`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 60193594966460162319774997373112005644450303415496697929754976735654535188776

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	129.513us	1	1	100.00
V1	smoke	aes_smoke	6.000s	89.975us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	96.881us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	99.374us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	9.000s	592.584us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	4.000s	164.367us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	73.450us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	99.374us	20	20	100.00
		aes_csr_aliasing	4.000s	164.367us	5	5	100.00
V1		TOTAL			105	106	99.06
V2	algorithm	aes_smoke	6.000s	89.975us	50	50	100.00
		aes_config_error	8.000s	313.776us	50	50	100.00
		aes_stress	4.983m	8.680ms	50	50	100.00
V2	key_length	aes_smoke	6.000s	89.975us	50	50	100.00
		aes_config_error	8.000s	313.776us	50	50	100.00
		aes_stress	4.983m	8.680ms	50	50	100.00
V2	back2back	aes_stress	4.983m	8.680ms	50	50	100.00
		aes_b2b	28.000s	343.533us	50	50	100.00
V2	backpressure	aes_stress	4.983m	8.680ms	50	50	100.00
V2	multi_message	aes_smoke	6.000s	89.975us	50	50	100.00
		aes_config_error	8.000s	313.776us	50	50	100.00
		aes_stress	4.983m	8.680ms	50	50	100.00
		aes_alert_reset	26.000s	1.951ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	13.000s	902.683us	50	50	100.00
		aes_config_error	8.000s	313.776us	50	50	100.00
		aes_alert_reset	26.000s	1.951ms	50	50	100.00
V2	trigger_clear_test	aes_clear	24.000s	1.294ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	34.000s	2.946ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	26.000s	1.951ms	50	50	100.00
V2	stress	aes_stress	4.983m	8.680ms	50	50	100.00
V2	sideload	aes_stress	4.983m	8.680ms	50	50	100.00
		aes_sideload	25.000s	2.584ms	50	50	100.00
V2	deinitialization	aes_deinit	16.000s	456.802us	50	50	100.00
V2	stress_all	aes_stress_all	8.417m	16.382ms	10	10	100.00
V2	alert_test	aes_alert_test	4.000s	59.537us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	7.000s	216.006us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	7.000s	216.006us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	96.881us	5	5	100.00
		aes_csr_rw	3.000s	99.374us	20	20	100.00
		aes_csr_aliasing	4.000s	164.367us	5	5	100.00
		aes_same_csr_outstanding	4.000s	168.569us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	96.881us	5	5	100.00
		aes_csr_rw	3.000s	99.374us	20	20	100.00
		aes_csr_aliasing	4.000s	164.367us	5	5	100.00
		aes_same_csr_outstanding	4.000s	168.569us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	47.000s	2.820ms	49	50	98.00
V2S	fault_inject	aes_fi	17.000s	539.711us	50	50	100.00
		aes_control_fi	48.000s	10.090ms	280	300	93.33
		aes_cipher_fi	46.000s	10.007ms	334	350	95.43
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	190.295us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	190.295us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	190.295us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	190.295us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	336.740us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	17.000s	2.958ms	5	5	100.00
		aes_tl_intg_err	5.000s	291.247us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	291.247us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	26.000s	1.951ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	190.295us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	6.000s	89.975us	50	50	100.00
		aes_stress	4.983m	8.680ms	50	50	100.00
		aes_alert_reset	26.000s	1.951ms	50	50	100.00
		aes_core_fi	1.433m	10.040ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	190.295us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	4.000s	53.743us	50	50	100.00
		aes_stress	4.983m	8.680ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	4.983m	8.680ms	50	50	100.00
		aes_sideload	25.000s	2.584ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	4.000s	53.743us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	4.000s	53.743us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	4.000s	53.743us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	4.000s	53.743us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	4.000s	53.743us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	4.983m	8.680ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	4.983m	8.680ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	17.000s	539.711us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	17.000s	539.711us	50	50	100.00
		aes_control_fi	48.000s	10.090ms	280	300	93.33
		aes_cipher_fi	46.000s	10.007ms	334	350	95.43
		aes_ctr_fi	6.000s	673.281us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	17.000s	539.711us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	17.000s	539.711us	50	50	100.00
		aes_control_fi	48.000s	10.090ms	280	300	93.33
		aes_cipher_fi	46.000s	10.007ms	334	350	95.43
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	46.000s	10.007ms	334	350	95.43
V2S	sec_cm_ctr_fsm_sparse	aes_fi	17.000s	539.711us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	17.000s	539.711us	50	50	100.00
		aes_control_fi	48.000s	10.090ms	280	300	93.33
		aes_ctr_fi	6.000s	673.281us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	17.000s	539.711us	50	50	100.00
		aes_control_fi	48.000s	10.090ms	280	300	93.33
		aes_cipher_fi	46.000s	10.007ms	334	350	95.43
		aes_ctr_fi	6.000s	673.281us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	26.000s	1.951ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	17.000s	539.711us	50	50	100.00
		aes_control_fi	48.000s	10.090ms	280	300	93.33
		aes_cipher_fi	46.000s	10.007ms	334	350	95.43
		aes_ctr_fi	6.000s	673.281us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	17.000s	539.711us	50	50	100.00
		aes_control_fi	48.000s	10.090ms	280	300	93.33
		aes_cipher_fi	46.000s	10.007ms	334	350	95.43
		aes_ctr_fi	6.000s	673.281us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	17.000s	539.711us	50	50	100.00
		aes_control_fi	48.000s	10.090ms	280	300	93.33
		aes_ctr_fi	6.000s	673.281us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	17.000s	539.711us	50	50	100.00
		aes_control_fi	48.000s	10.090ms	280	300	93.33
		aes_cipher_fi	46.000s	10.007ms	334	350	95.43
V2S		TOTAL			945	985	95.94
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	1.817m	11.865ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1551	1602	96.82

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	6	85.71
V2	13	13	13	100.00
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.56	98.90	97.23	99.45	95.90	97.64	100.00	98.96	96.61

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 21 failures:
- Test aes_control_fi has 14 failures.
  - 26.aes_control_fi.14882236775765675140157358490629974671723675580970411577745994596814077630744
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/26.aes_control_fi/latest/run.log
```
  Job ID: smart:34a0d1eb-a8c4-4b92-a167-c02d3fd85b95
```
  - 36.aes_control_fi.30337269891744163511147227836895743624259636426050714504835912371297950489120
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/36.aes_control_fi/latest/run.log
```
  Job ID: smart:835ad2be-6c1b-4916-9797-abfb07e14726
```
  - ... and 12 more failures.
- Test aes_cipher_fi has 7 failures.
  - 35.aes_cipher_fi.20376969559408242513920506717132048612004589320419385037948684679709530721273
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/35.aes_cipher_fi/latest/run.log
```
  Job ID: smart:df0f58ae-84f4-4632-9097-07b23e738b3d
```
  - 85.aes_cipher_fi.90238706062815761638610882439274383728763619250594126740813033937345342969128
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/85.aes_cipher_fi/latest/run.log
```
  Job ID: smart:2020a404-2d73-4a84-888b-5dc664cd9d54
```
  - ... and 5 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 10 failures:

Test aes_stress_all_with_rand_reset has 10 failures.

0.aes_stress_all_with_rand_reset.73205999979904008093191329439156272947977706322749855887692246862513263611356
Line 925, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 9467589836 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 9467589836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.64153757922222164531512241300089156338174021825031120101451840795121793287288
Line 1586, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3976473074 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3976473074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_cipher_fi has 9 failures.
  - 20.aes_cipher_fi.17855361425964104716562489297313393387893760302559533448352301314355884259952
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/20.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10006791302 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006791302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 39.aes_cipher_fi.106079372667863701287967119021615063333469122130541578526522910950476783667340
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/39.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10020013881 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10020013881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 6 failures:
- Test aes_control_fi has 6 failures.
  - 18.aes_control_fi.44607076837431195413362752912051804683289479965743896480519456613731308795229
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/18.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10019911245 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10019911245 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 29.aes_control_fi.109623359460481446544020040077747825266772449069274542088097039035829418643344
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/29.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10090378511 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10090378511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 19.aes_core_fi.47763158276020453265625348194760955284186628920206563538651878396610354361861
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/19.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10039711448 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10039711448 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 45.aes_core_fi.18919285805828686941582328121075413983170408840392074102234608345461806403166
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/45.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10022584776 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10022584776 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:830) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_csr_mem_rw_with_rand_reset has 1 failures.
  - 2.aes_csr_mem_rw_with_rand_reset.70456016710661758086767217451416627669403424962969254598216912268719792620667
    Line 285, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 111775928 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 111775928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 3.aes_core_fi.33872115415248279043015268546520785722740851599334845542705610541117607178389
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10023671207 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10023671207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (aes_reseed_vseq.sv:40) [aes_reseed_vseq] Check failed request_seen | finished_all_msgs == *'b* (* [*] vs * [*]) has 1 failures:
- Test aes_reseed has 1 failures.
  - 28.aes_reseed.79102008288068404673902352773661703009317211897427256374607116150973416323203
    Line 788, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/28.aes_reseed/latest/run.log
```
  UVM_FATAL @  40350249 ps: (aes_reseed_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen | finished_all_msgs == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @  40350249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```