AES/MASKED Simulation Results

Thursday July 25 2024 23:02:35 UTC

GitHub Revision: `a47820eb4c`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 42717125255024305080795900498886328747526075712606813106869971419713539568742

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	117.300us	1	1	100.00
V1	smoke	aes_smoke	29.000s	890.172us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	8.000s	80.430us	5	5	100.00
V1	csr_rw	aes_csr_rw	8.000s	108.336us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	8.000s	5.237ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	166.789us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	7.000s	63.956us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	8.000s	108.336us	20	20	100.00
		aes_csr_aliasing	5.000s	166.789us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	29.000s	890.172us	50	50	100.00
		aes_config_error	21.000s	756.260us	50	50	100.00
		aes_stress	31.000s	3.213ms	50	50	100.00
V2	key_length	aes_smoke	29.000s	890.172us	50	50	100.00
		aes_config_error	21.000s	756.260us	50	50	100.00
		aes_stress	31.000s	3.213ms	50	50	100.00
V2	back2back	aes_stress	31.000s	3.213ms	50	50	100.00
		aes_b2b	39.000s	536.885us	50	50	100.00
V2	backpressure	aes_stress	31.000s	3.213ms	50	50	100.00
V2	multi_message	aes_smoke	29.000s	890.172us	50	50	100.00
		aes_config_error	21.000s	756.260us	50	50	100.00
		aes_stress	31.000s	3.213ms	50	50	100.00
		aes_alert_reset	35.000s	1.590ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	9.000s	146.876us	50	50	100.00
		aes_config_error	21.000s	756.260us	50	50	100.00
		aes_alert_reset	35.000s	1.590ms	50	50	100.00
V2	trigger_clear_test	aes_clear	2.667m	4.349ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	12.000s	677.254us	1	1	100.00
V2	reset_recovery	aes_alert_reset	35.000s	1.590ms	50	50	100.00
V2	stress	aes_stress	31.000s	3.213ms	50	50	100.00
V2	sideload	aes_stress	31.000s	3.213ms	50	50	100.00
		aes_sideload	18.000s	647.009us	50	50	100.00
V2	deinitialization	aes_deinit	17.000s	558.281us	50	50	100.00
V2	stress_all	aes_stress_all	1.533m	19.724ms	10	10	100.00
V2	alert_test	aes_alert_test	24.000s	65.988us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	5.000s	115.330us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	5.000s	115.330us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	8.000s	80.430us	5	5	100.00
		aes_csr_rw	8.000s	108.336us	20	20	100.00
		aes_csr_aliasing	5.000s	166.789us	5	5	100.00
		aes_same_csr_outstanding	18.000s	117.932us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	8.000s	80.430us	5	5	100.00
		aes_csr_rw	8.000s	108.336us	20	20	100.00
		aes_csr_aliasing	5.000s	166.789us	5	5	100.00
		aes_same_csr_outstanding	18.000s	117.932us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	21.000s	299.087us	50	50	100.00
V2S	fault_inject	aes_fi	17.000s	102.804us	50	50	100.00
		aes_control_fi	48.000s	10.038ms	285	300	95.00
		aes_cipher_fi	43.000s	10.020ms	336	350	96.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	8.000s	123.480us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	8.000s	123.480us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	8.000s	123.480us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	8.000s	123.480us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	13.000s	58.957us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	8.000s	1.922ms	5	5	100.00
		aes_tl_intg_err	9.000s	206.936us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	9.000s	206.936us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	35.000s	1.590ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	8.000s	123.480us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	29.000s	890.172us	50	50	100.00
		aes_stress	31.000s	3.213ms	50	50	100.00
		aes_alert_reset	35.000s	1.590ms	50	50	100.00
		aes_core_fi	3.817m	10.023ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	8.000s	123.480us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	8.000s	84.089us	50	50	100.00
		aes_stress	31.000s	3.213ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	31.000s	3.213ms	50	50	100.00
		aes_sideload	18.000s	647.009us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	8.000s	84.089us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	8.000s	84.089us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	8.000s	84.089us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	8.000s	84.089us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	8.000s	84.089us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	31.000s	3.213ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	31.000s	3.213ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	17.000s	102.804us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	17.000s	102.804us	50	50	100.00
		aes_control_fi	48.000s	10.038ms	285	300	95.00
		aes_cipher_fi	43.000s	10.020ms	336	350	96.00
		aes_ctr_fi	8.000s	291.443us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	17.000s	102.804us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	17.000s	102.804us	50	50	100.00
		aes_control_fi	48.000s	10.038ms	285	300	95.00
		aes_cipher_fi	43.000s	10.020ms	336	350	96.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	43.000s	10.020ms	336	350	96.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	17.000s	102.804us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	17.000s	102.804us	50	50	100.00
		aes_control_fi	48.000s	10.038ms	285	300	95.00
		aes_ctr_fi	8.000s	291.443us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	17.000s	102.804us	50	50	100.00
		aes_control_fi	48.000s	10.038ms	285	300	95.00
		aes_cipher_fi	43.000s	10.020ms	336	350	96.00
		aes_ctr_fi	8.000s	291.443us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	35.000s	1.590ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	17.000s	102.804us	50	50	100.00
		aes_control_fi	48.000s	10.038ms	285	300	95.00
		aes_cipher_fi	43.000s	10.020ms	336	350	96.00
		aes_ctr_fi	8.000s	291.443us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	17.000s	102.804us	50	50	100.00
		aes_control_fi	48.000s	10.038ms	285	300	95.00
		aes_cipher_fi	43.000s	10.020ms	336	350	96.00
		aes_ctr_fi	8.000s	291.443us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	17.000s	102.804us	50	50	100.00
		aes_control_fi	48.000s	10.038ms	285	300	95.00
		aes_ctr_fi	8.000s	291.443us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	17.000s	102.804us	50	50	100.00
		aes_control_fi	48.000s	10.038ms	285	300	95.00
		aes_cipher_fi	43.000s	10.020ms	336	350	96.00
V2S		TOTAL			953	985	96.75
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	6.750m	9.831ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1560	1602	97.38

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.36	98.56	96.34	99.45	95.71	97.64	100.00	98.96	96.61

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 18 failures:
- Test aes_cipher_fi has 7 failures.
  - 2.aes_cipher_fi.131665038293962753794166986822708142113802245350260407896858165343756288117
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_cipher_fi/latest/run.log
```
  Job ID: smart:3c45f8b8-878f-436f-bbed-6dce9221aa74
```
  - 94.aes_cipher_fi.59080543052941528651818300078905386255635568132140981235244940194127637009843
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/94.aes_cipher_fi/latest/run.log
```
  Job ID: smart:e54bce9b-6225-4fd4-9883-6d4ee96d362f
```
  - ... and 5 more failures.
- Test aes_control_fi has 11 failures.
  - 44.aes_control_fi.82172263649107518295819670260021147937728841872903861159261469190325954082297
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/44.aes_control_fi/latest/run.log
```
  Job ID: smart:f519be05-e8de-42ea-9575-9d8fe52f6fa0
```
  - 55.aes_control_fi.97054352223239971238877280577328159032036479499730428358095635635533574749744
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/55.aes_control_fi/latest/run.log
```
  Job ID: smart:2b7cf0f1-96f1-4493-9d38-0ea3357a9c3a
```
  - ... and 9 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_cipher_fi has 7 failures.
  - 36.aes_cipher_fi.11106465824181446494520000659595459264405123676220862398738597362973918894008
    Line 327, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/36.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10023179259 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10023179259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 73.aes_cipher_fi.1013221950881115137424524999861823874323105148887636100374555189594346276197
    Line 325, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/73.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10051594563 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10051594563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

0.aes_stress_all_with_rand_reset.74668236607141449417834290718146788772695477462809970344343024647366594001325
Line 420, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 976982203 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 976982203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.102254259988159619008241407806369366302695992530980797274750320698649384093660
Line 773, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4996108329 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 4996108329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_control_fi has 4 failures.
  - 266.aes_control_fi.82043281889674423149932862458471461388122413573841642076258332558869759277417
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/266.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10037748389 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10037748389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 273.aes_control_fi.21533517143971247423044587662417510846350123202240205402378466137421258337890
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/273.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10016851774 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10016851774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 2 failures:

Test aes_stress_all_with_rand_reset has 2 failures.

6.aes_stress_all_with_rand_reset.54153056849105456206702376079519844531731956802484455989763043872803976487974
Line 969, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 411782471 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 411782471 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.aes_stress_all_with_rand_reset.26944216932034614243481545167681897155736166163784423785662626340591271093954
Line 1346, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 755699256 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 755699256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 17.aes_core_fi.19347981475745406036987041475570429290278985754163836143276751428595245655971
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/17.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10057107313 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10057107313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 47.aes_core_fi.25912341247079320104722366293061489619655466830844069057670435109074123386231
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/47.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10018099877 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10018099877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:840) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 5.aes_stress_all_with_rand_reset.54255857759731377729669327473451343042362953743673219738811387731902786287783
    Line 448, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9830618402 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 9830618402 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:840) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 9.aes_stress_all_with_rand_reset.84936253246793662612839753399701570804341011706054533028582998518690497292408
    Line 1474, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/9.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4358714353 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 4358714353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 60.aes_core_fi.107999491556723910414952717816474040899748973300361119274057614076821456991910
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/60.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10022916339 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0xd65b4e84, Comparison=CompareOpEq, exp_data=0x0, call_count=7)
  UVM_INFO @ 10022916339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```