AES/MASKED Simulation Results

Saturday February 08 2025 05:05:54 UTC

GitHub Revision: `9f20940d49`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 88344288495849993302635329522992994622996067932062874150778031027723701018040

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	69.460us	1	1	100.00
V1	smoke	aes_smoke	27.000s	171.704us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	14.000s	124.375us	5	5	100.00
V1	csr_rw	aes_csr_rw	28.000s	107.990us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	18.000s	586.590us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	15.000s	205.475us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	28.000s	65.485us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	28.000s	107.990us	20	20	100.00
		aes_csr_aliasing	15.000s	205.475us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	27.000s	171.704us	50	50	100.00
		aes_config_error	35.000s	105.286us	50	50	100.00
		aes_stress	1.167m	1.374ms	50	50	100.00
V2	key_length	aes_smoke	27.000s	171.704us	50	50	100.00
		aes_config_error	35.000s	105.286us	50	50	100.00
		aes_stress	1.167m	1.374ms	50	50	100.00
V2	back2back	aes_stress	1.167m	1.374ms	50	50	100.00
		aes_b2b	55.000s	689.254us	50	50	100.00
V2	backpressure	aes_stress	1.167m	1.374ms	50	50	100.00
V2	multi_message	aes_smoke	27.000s	171.704us	50	50	100.00
		aes_config_error	35.000s	105.286us	50	50	100.00
		aes_stress	1.167m	1.374ms	50	50	100.00
		aes_alert_reset	2.350m	6.112ms	48	50	96.00
V2	failure_test	aes_man_cfg_err	33.000s	87.758us	50	50	100.00
		aes_config_error	35.000s	105.286us	50	50	100.00
		aes_alert_reset	2.350m	6.112ms	48	50	96.00
V2	trigger_clear_test	aes_clear	45.000s	6.278ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	12.000s	1.191ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	2.350m	6.112ms	48	50	96.00
V2	stress	aes_stress	1.167m	1.374ms	50	50	100.00
V2	sideload	aes_stress	1.167m	1.374ms	50	50	100.00
		aes_sideload	39.000s	1.904ms	50	50	100.00
V2	deinitialization	aes_deinit	32.000s	393.168us	50	50	100.00
V2	stress_all	aes_stress_all	3.033m	7.055ms	10	10	100.00
V2	alert_test	aes_alert_test	26.000s	53.275us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	31.000s	394.526us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	31.000s	394.526us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	14.000s	124.375us	5	5	100.00
		aes_csr_rw	28.000s	107.990us	20	20	100.00
		aes_csr_aliasing	15.000s	205.475us	5	5	100.00
		aes_same_csr_outstanding	28.000s	63.654us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	14.000s	124.375us	5	5	100.00
		aes_csr_rw	28.000s	107.990us	20	20	100.00
		aes_csr_aliasing	15.000s	205.475us	5	5	100.00
		aes_same_csr_outstanding	28.000s	63.654us	20	20	100.00
V2		TOTAL			499	501	99.60
V2S	reseeding	aes_reseed	34.000s	363.328us	50	50	100.00
V2S	fault_inject	aes_fi	32.000s	207.052us	50	50	100.00
		aes_control_fi	47.000s	10.012ms	281	300	93.67
		aes_cipher_fi	59.000s	10.014ms	344	350	98.29
V2S	shadow_reg_update_error	aes_shadow_reg_errors	27.000s	82.052us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	27.000s	82.052us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	27.000s	82.052us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	27.000s	82.052us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	25.000s	80.898us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	9.000s	1.915ms	5	5	100.00
		aes_tl_intg_err	27.000s	166.814us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	27.000s	166.814us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	2.350m	6.112ms	48	50	96.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	27.000s	82.052us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	27.000s	171.704us	50	50	100.00
		aes_stress	1.167m	1.374ms	50	50	100.00
		aes_alert_reset	2.350m	6.112ms	48	50	96.00
		aes_core_fi	40.000s	10.011ms	69	70	98.57
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	27.000s	82.052us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	33.000s	69.530us	50	50	100.00
		aes_stress	1.167m	1.374ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	1.167m	1.374ms	50	50	100.00
		aes_sideload	39.000s	1.904ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	33.000s	69.530us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	33.000s	69.530us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	33.000s	69.530us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	33.000s	69.530us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	33.000s	69.530us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	1.167m	1.374ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	1.167m	1.374ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	32.000s	207.052us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	32.000s	207.052us	50	50	100.00
		aes_control_fi	47.000s	10.012ms	281	300	93.67
		aes_cipher_fi	59.000s	10.014ms	344	350	98.29
		aes_ctr_fi	31.000s	84.260us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	32.000s	207.052us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	32.000s	207.052us	50	50	100.00
		aes_control_fi	47.000s	10.012ms	281	300	93.67
		aes_cipher_fi	59.000s	10.014ms	344	350	98.29
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	59.000s	10.014ms	344	350	98.29
V2S	sec_cm_ctr_fsm_sparse	aes_fi	32.000s	207.052us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	32.000s	207.052us	50	50	100.00
		aes_control_fi	47.000s	10.012ms	281	300	93.67
		aes_ctr_fi	31.000s	84.260us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	32.000s	207.052us	50	50	100.00
		aes_control_fi	47.000s	10.012ms	281	300	93.67
		aes_cipher_fi	59.000s	10.014ms	344	350	98.29
		aes_ctr_fi	31.000s	84.260us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	2.350m	6.112ms	48	50	96.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	32.000s	207.052us	50	50	100.00
		aes_control_fi	47.000s	10.012ms	281	300	93.67
		aes_cipher_fi	59.000s	10.014ms	344	350	98.29
		aes_ctr_fi	31.000s	84.260us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	32.000s	207.052us	50	50	100.00
		aes_control_fi	47.000s	10.012ms	281	300	93.67
		aes_cipher_fi	59.000s	10.014ms	344	350	98.29
		aes_ctr_fi	31.000s	84.260us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	32.000s	207.052us	50	50	100.00
		aes_control_fi	47.000s	10.012ms	281	300	93.67
		aes_ctr_fi	31.000s	84.260us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	32.000s	207.052us	50	50	100.00
		aes_control_fi	47.000s	10.012ms	281	300	93.67
		aes_cipher_fi	59.000s	10.014ms	344	350	98.29
V2S		TOTAL			959	985	97.36
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	3.367m	19.813ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1564	1602	97.63

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	12	92.31
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.38	98.57	96.37	99.45	95.83	97.72	100.00	99.11	96.61

Failure Buckets

Job timed out after * minutes has 13 failures:
- Test aes_control_fi has 11 failures.
  - 37.aes_control_fi.54909518888633156132738010531944124342834809805265850815147513505694847647540
    Log /workspaces/repo/scratch/os_regression/aes_masked-sim-xcelium/37.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 41.aes_control_fi.13891433500577832322449785742785529456888872495188281440016596116278781052154
    Log /workspaces/repo/scratch/os_regression/aes_masked-sim-xcelium/41.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 9 more failures.
- Test aes_cipher_fi has 2 failures.
  - 314.aes_cipher_fi.62771050420482633360646254381960428530430644994175271821192021406457307255933
    Log /workspaces/repo/scratch/os_regression/aes_masked-sim-xcelium/314.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 318.aes_cipher_fi.86571006872142698273927058037921107220385096585699497981000416008945759442908
    Log /workspaces/repo/scratch/os_regression/aes_masked-sim-xcelium/318.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 9 failures:

Test aes_stress_all_with_rand_reset has 9 failures.

0.aes_stress_all_with_rand_reset.39638209852193455042395283505850392236112373850031111687674718232481922622626
Line 1341, in log /workspaces/repo/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3216233728 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3216233728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.75568628258598484301297826254007080101206524199582608763853134255442474751840
Line 1352, in log /workspaces/repo/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3655245872 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3655245872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 8 failures:
- Test aes_control_fi has 8 failures.
  - 27.aes_control_fi.63371310676711852302558878111146831475042976958071420053970819865790298188501
    Line 128, in log /workspaces/repo/scratch/os_regression/aes_masked-sim-xcelium/27.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10051966238 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10051966238 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 58.aes_control_fi.76252976565494662402210690408079415107647942497931690527701549026360931528129
    Line 136, in log /workspaces/repo/scratch/os_regression/aes_masked-sim-xcelium/58.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10026935394 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10026935394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_cipher_fi has 4 failures.
  - 18.aes_cipher_fi.32452425645701772892765577620028559671523639470519005702567227691204199616384
    Line 127, in log /workspaces/repo/scratch/os_regression/aes_masked-sim-xcelium/18.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10013775131 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013775131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 28.aes_cipher_fi.36223647473766909654544965979236143117836040497353406304293719002654757996083
    Line 133, in log /workspaces/repo/scratch/os_regression/aes_masked-sim-xcelium/28.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10010304462 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010304462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression/aes_masked-sim-xcelium/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 2 failures:

Test aes_alert_reset has 2 failures.

7.aes_alert_reset.87991480218864024152917283043047631871751790481922119139004584847085738890675
Line 1569, in log /workspaces/repo/scratch/os_regression/aes_masked-sim-xcelium/7.aes_alert_reset/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression/aes_masked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 18579962 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 18538295 PS)
  UVM_ERROR @  18579962 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @  18579962 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

45.aes_alert_reset.106900879505188164266862482956272194843166375049767639264972302055315282687349
Line 4115, in log /workspaces/repo/scratch/os_regression/aes_masked-sim-xcelium/45.aes_alert_reset/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression/aes_masked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 10168055 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 10158055 PS)
        ($past(iv_q) != $past(state_done_transposed, 2) ^ $past(data_in_prev_q, 2)))
                                                                                   |
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression/aes_masked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 10168055 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 10158055 PS)
  UVM_ERROR @  10168055 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut

UVM_ERROR (cip_base_vseq.sv:837) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 9.aes_stress_all_with_rand_reset.37924801892929121163641113847698056675957765851113530709384732914042785645179
    Line 253, in log /workspaces/repo/scratch/os_regression/aes_masked-sim-xcelium/9.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 19813338358 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 19813338358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 66.aes_core_fi.52045582827744956935528197411460747235335654868600087567331872224994490613049
    Line 135, in log /workspaces/repo/scratch/os_regression/aes_masked-sim-xcelium/66.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10011238429 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011238429 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```