AES/MASKED Simulation Results

Wednesday November 22 2023 20:02:38 UTC

GitHub Revision: 4002b28ec4

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 56541452733628775295814943325285397402671097056517970046183331126493552547969

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	103.398us	1	1	100.00
V1	smoke	aes_smoke	5.000s	104.633us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	73.586us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	65.112us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	7.000s	656.547us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	4.000s	188.636us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	72.281us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	65.112us	20	20	100.00
		aes_csr_aliasing	4.000s	188.636us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	5.000s	104.633us	50	50	100.00
		aes_config_error	6.000s	181.692us	50	50	100.00
		aes_stress	10.000s	108.077us	50	50	100.00
V2	key_length	aes_smoke	5.000s	104.633us	50	50	100.00
		aes_config_error	6.000s	181.692us	50	50	100.00
		aes_stress	10.000s	108.077us	50	50	100.00
V2	back2back	aes_stress	10.000s	108.077us	50	50	100.00
		aes_b2b	14.000s	405.396us	50	50	100.00
V2	backpressure	aes_stress	10.000s	108.077us	50	50	100.00
V2	multi_message	aes_smoke	5.000s	104.633us	50	50	100.00
		aes_config_error	6.000s	181.692us	50	50	100.00
		aes_stress	10.000s	108.077us	50	50	100.00
		aes_alert_reset	10.000s	275.811us	50	50	100.00
V2	failure_test	aes_man_cfg_err	5.000s	90.398us	50	50	100.00
		aes_config_error	6.000s	181.692us	50	50	100.00
		aes_alert_reset	10.000s	275.811us	50	50	100.00
V2	trigger_clear_test	aes_clear	10.000s	177.692us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	11.000s	876.521us	1	1	100.00
V2	reset_recovery	aes_alert_reset	10.000s	275.811us	50	50	100.00
V2	stress	aes_stress	10.000s	108.077us	50	50	100.00
V2	sideload	aes_stress	10.000s	108.077us	50	50	100.00
		aes_sideload	5.000s	122.045us	50	50	100.00
V2	deinitialization	aes_deinit	9.000s	158.927us	50	50	100.00
V2	stress_all	aes_stress_all	31.000s	1.589ms	10	10	100.00
V2	alert_test	aes_alert_test	8.000s	68.993us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	4.000s	160.958us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	4.000s	160.958us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	73.586us	5	5	100.00
		aes_csr_rw	3.000s	65.112us	20	20	100.00
		aes_csr_aliasing	4.000s	188.636us	5	5	100.00
		aes_same_csr_outstanding	4.000s	123.670us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	73.586us	5	5	100.00
		aes_csr_rw	3.000s	65.112us	20	20	100.00
		aes_csr_aliasing	4.000s	188.636us	5	5	100.00
		aes_same_csr_outstanding	4.000s	123.670us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	12.000s	322.584us	50	50	100.00
V2S	fault_inject	aes_fi	11.000s	191.340us	50	50	100.00
		aes_control_fi			0	300	0.00
		aes_cipher_fi	8.000s	101.045us	350	350	100.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	90.806us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	90.806us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	90.806us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	90.806us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	121.552us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	8.000s	707.496us	5	5	100.00
		aes_tl_intg_err	5.000s	216.483us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	216.483us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	10.000s	275.811us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	90.806us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	5.000s	104.633us	50	50	100.00
		aes_stress	10.000s	108.077us	50	50	100.00
		aes_alert_reset	10.000s	275.811us	50	50	100.00
		aes_core_fi	9.000s	186.045us	70	70	100.00
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	90.806us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	8.000s	97.809us	50	50	100.00
		aes_stress	10.000s	108.077us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	10.000s	108.077us	50	50	100.00
		aes_sideload	5.000s	122.045us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	8.000s	97.809us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	8.000s	97.809us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	8.000s	97.809us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	8.000s	97.809us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	8.000s	97.809us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	10.000s	108.077us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	10.000s	108.077us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	11.000s	191.340us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	11.000s	191.340us	50	50	100.00
		aes_control_fi			0	300	0.00
		aes_cipher_fi	8.000s	101.045us	350	350	100.00
		aes_ctr_fi	5.000s	123.280us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	11.000s	191.340us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	11.000s	191.340us	50	50	100.00
		aes_control_fi			0	300	0.00
		aes_cipher_fi	8.000s	101.045us	350	350	100.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	8.000s	101.045us	350	350	100.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	11.000s	191.340us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	11.000s	191.340us	50	50	100.00
		aes_control_fi			0	300	0.00
		aes_ctr_fi	5.000s	123.280us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	11.000s	191.340us	50	50	100.00
		aes_control_fi			0	300	0.00
		aes_cipher_fi	8.000s	101.045us	350	350	100.00
		aes_ctr_fi	5.000s	123.280us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	10.000s	275.811us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	11.000s	191.340us	50	50	100.00
		aes_control_fi			0	300	0.00
		aes_cipher_fi	8.000s	101.045us	350	350	100.00
		aes_ctr_fi	5.000s	123.280us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	11.000s	191.340us	50	50	100.00
		aes_control_fi			0	300	0.00
		aes_cipher_fi	8.000s	101.045us	350	350	100.00
		aes_ctr_fi	5.000s	123.280us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	11.000s	191.340us	50	50	100.00
		aes_control_fi			0	300	0.00
		aes_ctr_fi	5.000s	123.280us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	11.000s	191.340us	50	50	100.00
		aes_control_fi			0	300	0.00
		aes_cipher_fi	8.000s	101.045us	350	350	100.00
V2S		TOTAL			685	985	69.54
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	23.000s	1.062ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1292	1602	80.65

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	10	90.91
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
95.07	95.93	91.19	96.94	90.54	95.60	93.33	98.82	76.88

Failure Buckets

• Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 300 failures:
  • Test aes_control_fi has 300 failures.

    • 0.aes_control_fi.3717957500462085826496279422077228121722984813340916758555797533850130257867
      Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_control_fi/latest/run.log

        Job ID: smart:fbe8430e-fec8-48e8-a414-dafe7195c387
      

    • 1.aes_control_fi.92000036743313327927404245519554329150859108057945727466030238177215101841093
      Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_control_fi/latest/run.log

        Job ID: smart:c6fb4b65-17c4-463c-b973-21ab5ca2a765
      

    • ... and 298 more failures.

• Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 10 failures:
  • Test aes_stress_all_with_rand_reset has 10 failures.

    • 0.aes_stress_all_with_rand_reset.46443568003962022812270728555327640370399568568135801783010306661840311999669
      Line 602, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1062102162 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
        UVM_INFO @ 1062102162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.aes_stress_all_with_rand_reset.89608012400627632658030586256387109077865236500666683631582472866555795888705
      Line 602, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1062102162 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
        UVM_INFO @ 1062102162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 8 more failures.

Past Results

• Latest
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• 2023.10.30_18.05.13
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• 2023.10.23_18.05.04
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