AES/MASKED Simulation Results

Monday October 14 2024 17:26:15 UTC

GitHub Revision: `12e3b8572e`

Branch: os_regression_2024_10_14

Simulator: XCELIUM

Build randomization enabled with --build-seed 85025606402499621082521464627961092918263397067038954055071960501195381950243

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	1.017m	235.623us	1	1	100.00
V1	smoke	aes_smoke	1.517m	97.612us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	16.000s	76.747us	5	5	100.00
V1	csr_rw	aes_csr_rw	28.000s	63.420us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	35.000s	906.395us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	28.000s	164.493us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	27.000s	138.709us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	28.000s	63.420us	20	20	100.00
		aes_csr_aliasing	28.000s	164.493us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	1.517m	97.612us	50	50	100.00
		aes_config_error	2.817m	5.388ms	50	50	100.00
		aes_stress	1.983m	87.401us	50	50	100.00
V2	key_length	aes_smoke	1.517m	97.612us	50	50	100.00
		aes_config_error	2.817m	5.388ms	50	50	100.00
		aes_stress	1.983m	87.401us	50	50	100.00
V2	back2back	aes_stress	1.983m	87.401us	50	50	100.00
		aes_b2b	1.850m	194.110us	50	50	100.00
V2	backpressure	aes_stress	1.983m	87.401us	50	50	100.00
V2	multi_message	aes_smoke	1.517m	97.612us	50	50	100.00
		aes_config_error	2.817m	5.388ms	50	50	100.00
		aes_stress	1.983m	87.401us	50	50	100.00
		aes_alert_reset	1.900m	177.414us	50	50	100.00
V2	failure_test	aes_man_cfg_err	2.350m	95.598us	50	50	100.00
		aes_config_error	2.817m	5.388ms	50	50	100.00
		aes_alert_reset	1.900m	177.414us	50	50	100.00
V2	trigger_clear_test	aes_clear	1.667m	84.121us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	24.000s	535.931us	1	1	100.00
V2	reset_recovery	aes_alert_reset	1.900m	177.414us	50	50	100.00
V2	stress	aes_stress	1.983m	87.401us	50	50	100.00
V2	sideload	aes_stress	1.983m	87.401us	50	50	100.00
		aes_sideload	1.800m	77.237us	50	50	100.00
V2	deinitialization	aes_deinit	2.583m	219.176us	50	50	100.00
V2	stress_all	aes_stress_all	1.350m	1.692ms	10	10	100.00
V2	alert_test	aes_alert_test	1.917m	54.204us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	28.000s	76.653us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	28.000s	76.653us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	16.000s	76.747us	5	5	100.00
		aes_csr_rw	28.000s	63.420us	20	20	100.00
		aes_csr_aliasing	28.000s	164.493us	5	5	100.00
		aes_same_csr_outstanding	28.000s	302.014us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	16.000s	76.747us	5	5	100.00
		aes_csr_rw	28.000s	63.420us	20	20	100.00
		aes_csr_aliasing	28.000s	164.493us	5	5	100.00
		aes_same_csr_outstanding	28.000s	302.014us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	2.033m	83.872us	50	50	100.00
V2S	fault_inject	aes_fi	1.833m	1.085ms	50	50	100.00
		aes_control_fi	59.000s	78.277us	253	300	84.33
		aes_cipher_fi	59.000s	53.454us	320	350	91.43
V2S	shadow_reg_update_error	aes_shadow_reg_errors	29.000s	59.312us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	29.000s	59.312us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	29.000s	59.312us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	29.000s	59.312us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	29.000s	69.047us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	1.317m	3.249ms	5	5	100.00
		aes_tl_intg_err	28.000s	131.759us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	28.000s	131.759us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	1.900m	177.414us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	29.000s	59.312us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	1.517m	97.612us	50	50	100.00
		aes_stress	1.983m	87.401us	50	50	100.00
		aes_alert_reset	1.900m	177.414us	50	50	100.00
		aes_core_fi	4.183m	10.015ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	29.000s	59.312us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	2.033m	68.699us	50	50	100.00
		aes_stress	1.983m	87.401us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	1.983m	87.401us	50	50	100.00
		aes_sideload	1.800m	77.237us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	2.033m	68.699us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	2.033m	68.699us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	2.033m	68.699us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	2.033m	68.699us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	2.033m	68.699us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	1.983m	87.401us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	1.983m	87.401us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	1.833m	1.085ms	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	1.833m	1.085ms	50	50	100.00
		aes_control_fi	59.000s	78.277us	253	300	84.33
		aes_cipher_fi	59.000s	53.454us	320	350	91.43
		aes_ctr_fi	1.000m	56.108us	47	50	94.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	1.833m	1.085ms	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	1.833m	1.085ms	50	50	100.00
		aes_control_fi	59.000s	78.277us	253	300	84.33
		aes_cipher_fi	59.000s	53.454us	320	350	91.43
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	59.000s	53.454us	320	350	91.43
V2S	sec_cm_ctr_fsm_sparse	aes_fi	1.833m	1.085ms	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	1.833m	1.085ms	50	50	100.00
		aes_control_fi	59.000s	78.277us	253	300	84.33
		aes_ctr_fi	1.000m	56.108us	47	50	94.00
V2S	sec_cm_ctrl_sparse	aes_fi	1.833m	1.085ms	50	50	100.00
		aes_control_fi	59.000s	78.277us	253	300	84.33
		aes_cipher_fi	59.000s	53.454us	320	350	91.43
		aes_ctr_fi	1.000m	56.108us	47	50	94.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	1.900m	177.414us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	1.833m	1.085ms	50	50	100.00
		aes_control_fi	59.000s	78.277us	253	300	84.33
		aes_cipher_fi	59.000s	53.454us	320	350	91.43
		aes_ctr_fi	1.000m	56.108us	47	50	94.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	1.833m	1.085ms	50	50	100.00
		aes_control_fi	59.000s	78.277us	253	300	84.33
		aes_cipher_fi	59.000s	53.454us	320	350	91.43
		aes_ctr_fi	1.000m	56.108us	47	50	94.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	1.833m	1.085ms	50	50	100.00
		aes_control_fi	59.000s	78.277us	253	300	84.33
		aes_ctr_fi	1.000m	56.108us	47	50	94.00
V2S	sec_cm_data_reg_local_esc	aes_fi	1.833m	1.085ms	50	50	100.00
		aes_control_fi	59.000s	78.277us	253	300	84.33
		aes_cipher_fi	59.000s	53.454us	320	350	91.43
V2S		TOTAL			902	985	91.57
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	1.467m	1.170ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1509	1602	94.19

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.37	98.55	96.32	99.43	95.80	97.72	97.78	99.11	98.00

Failure Buckets

Job timed out after * minutes has 72 failures:
- Test aes_control_fi has 44 failures.
  - 4.aes_control_fi.61735814830508952120109917726903956543457892645794002814075865014208057497835
    Log /workspaces/repo/scratch/os_regression_2024_10_14/aes_masked-sim-xcelium/4.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 10.aes_control_fi.4939683315997511343019252702834698680938567160399596840570966582688402938102
    Log /workspaces/repo/scratch/os_regression_2024_10_14/aes_masked-sim-xcelium/10.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 42 more failures.
- Test aes_cipher_fi has 25 failures.
  - 4.aes_cipher_fi.110505244481623928588779009445680571950791857247478681098461396067680504381764
    Log /workspaces/repo/scratch/os_regression_2024_10_14/aes_masked-sim-xcelium/4.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 18.aes_cipher_fi.16416121536849455888479449740029909948249351119515116133072580357525965117595
    Log /workspaces/repo/scratch/os_regression_2024_10_14/aes_masked-sim-xcelium/18.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 23 more failures.
- Test aes_ctr_fi has 3 failures.
  - 18.aes_ctr_fi.59502308637138033115589046941634419767334264954110912681938177929571095577457
    Log /workspaces/repo/scratch/os_regression_2024_10_14/aes_masked-sim-xcelium/18.aes_ctr_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 35.aes_ctr_fi.5101418897699706042143992185028130946741552582869860922689039316508233612722
    Log /workspaces/repo/scratch/os_regression_2024_10_14/aes_masked-sim-xcelium/35.aes_ctr_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 1 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 5 failures:
- Test aes_cipher_fi has 5 failures.
  - 11.aes_cipher_fi.69735856548973601889667733409294559447750403915452398231938336725208280049944
    Line 126, in log /workspaces/repo/scratch/os_regression_2024_10_14/aes_masked-sim-xcelium/11.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10006882414 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006882414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 101.aes_cipher_fi.95469300337677157142994942078994529553078871448087707257676695053640077990743
    Line 130, in log /workspaces/repo/scratch/os_regression_2024_10_14/aes_masked-sim-xcelium/101.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10006896995 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006896995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 4 failures:
- Test aes_stress_all_with_rand_reset has 4 failures.
  - 0.aes_stress_all_with_rand_reset.81048883240543754615466302443165967414474672537820769654971506778492342135694
    Line 174, in log /workspaces/repo/scratch/os_regression_2024_10_14/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  91532671 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  91532671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.aes_stress_all_with_rand_reset.102383652006099374336412771644554550989097724325079907451840611461865634880658
    Line 849, in log /workspaces/repo/scratch/os_regression_2024_10_14/aes_masked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 954835032 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 954835032 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 3 failures:

Test aes_stress_all_with_rand_reset has 3 failures.

1.aes_stress_all_with_rand_reset.84109869395077672949121660640844885695525373790094166178424828008688015465567
Line 440, in log /workspaces/repo/scratch/os_regression_2024_10_14/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 170639057 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 170639057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.31569445517104859172351681722204628625847433917073923748502247681509191103326
Line 416, in log /workspaces/repo/scratch/os_regression_2024_10_14/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 837966594 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 837966594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_control_fi has 3 failures.
  - 186.aes_control_fi.61713667607490658974804888616760581257382632822061389822196601144193973164986
    Line 142, in log /workspaces/repo/scratch/os_regression_2024_10_14/aes_masked-sim-xcelium/186.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10049738301 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10049738301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 191.aes_control_fi.113596057900994916193795074041515947974870401489621404387445332968053341252378
    Line 143, in log /workspaces/repo/scratch/os_regression_2024_10_14/aes_masked-sim-xcelium/191.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10055823173 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10055823173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 48.aes_core_fi.111452457282059755420987199906357379011677962983734944524387605616873456777309
    Line 133, in log /workspaces/repo/scratch/os_regression_2024_10_14/aes_masked-sim-xcelium/48.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10038022940 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10038022940 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 54.aes_core_fi.17538426851167544936050707113519016982761172420779365323985498294452693026331
    Line 130, in log /workspaces/repo/scratch/os_regression_2024_10_14/aes_masked-sim-xcelium/54.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10021218963 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10021218963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:868) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 3.aes_stress_all_with_rand_reset.101076820692123347160984202027179340216239702490454570086395763118415037007704
    Line 168, in log /workspaces/repo/scratch/os_regression_2024_10_14/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 786047126 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 786047126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 6.aes_stress_all_with_rand_reset.101015396308482016475278474602392199760337585952350700112034767516411931996982
    Line 209, in log /workspaces/repo/scratch/os_regression_2024_10_14/aes_masked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 118535273 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 118535273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 8.aes_stress_all_with_rand_reset.37991504605361181019136872631009193419193576820542642250291389827658595472608
    Line 316, in log /workspaces/repo/scratch/os_regression_2024_10_14/aes_masked-sim-xcelium/8.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1170363281 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 1170363281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 68.aes_core_fi.32487112695745198642214917605983684858238857841763959966545510488090794224551
    Line 125, in log /workspaces/repo/scratch/os_regression_2024_10_14/aes_masked-sim-xcelium/68.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10015190505 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x34bb8b84, Comparison=CompareOpEq, exp_data=0x0, call_count=8)
  UVM_INFO @ 10015190505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```