AES/MASKED Simulation Results

Tuesday May 30 2023 07:03:17 UTC

GitHub Revision: `f8b3c19a2`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 1284268927

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	68.046us	1	1	100.00
V1	smoke	aes_smoke	14.000s	373.598us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	52.425us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	59.003us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	6.000s	320.879us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	6.000s	460.912us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	74.751us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	59.003us	20	20	100.00
		aes_csr_aliasing	6.000s	460.912us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	14.000s	373.598us	50	50	100.00
		aes_config_error	24.000s	707.997us	50	50	100.00
		aes_stress	3.517m	2.680ms	50	50	100.00
V2	key_length	aes_smoke	14.000s	373.598us	50	50	100.00
		aes_config_error	24.000s	707.997us	50	50	100.00
		aes_stress	3.517m	2.680ms	50	50	100.00
V2	back2back	aes_stress	3.517m	2.680ms	50	50	100.00
		aes_b2b	46.000s	1.311ms	50	50	100.00
V2	backpressure	aes_stress	3.517m	2.680ms	50	50	100.00
V2	multi_message	aes_smoke	14.000s	373.598us	50	50	100.00
		aes_config_error	24.000s	707.997us	50	50	100.00
		aes_stress	3.517m	2.680ms	50	50	100.00
		aes_alert_reset	12.000s	242.485us	50	50	100.00
V2	failure_test	aes_config_error	24.000s	707.997us	50	50	100.00
		aes_alert_reset	12.000s	242.485us	50	50	100.00
		aes_man_cfg_err	7.000s	205.489us	50	50	100.00
V2	trigger_clear_test	aes_clear	46.000s	1.696ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	11.000s	373.769us	1	1	100.00
V2	reset_recovery	aes_alert_reset	12.000s	242.485us	50	50	100.00
V2	stress	aes_stress	3.517m	2.680ms	50	50	100.00
V2	sideload	aes_stress	3.517m	2.680ms	50	50	100.00
		aes_sideload	11.000s	347.074us	50	50	100.00
V2	deinitialization	aes_deinit	29.000s	991.453us	50	50	100.00
V2	alert_test	aes_alert_test	4.000s	52.692us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	5.000s	200.181us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	5.000s	200.181us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	52.425us	5	5	100.00
		aes_csr_rw	3.000s	59.003us	20	20	100.00
		aes_csr_aliasing	6.000s	460.912us	5	5	100.00
		aes_same_csr_outstanding	4.000s	159.105us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	52.425us	5	5	100.00
		aes_csr_rw	3.000s	59.003us	20	20	100.00
		aes_csr_aliasing	6.000s	460.912us	5	5	100.00
		aes_same_csr_outstanding	4.000s	159.105us	20	20	100.00
V2		TOTAL			491	491	100.00
V2S	reseeding	aes_reseed	2.217m	1.649ms	50	50	100.00
V2S	fault_inject	aes_fi	14.000s	697.629us	50	50	100.00
		aes_control_fi	47.000s	10.006ms	280	300	93.33
		aes_cipher_fi	45.000s	10.010ms	338	350	96.57
V2S	shadow_reg_update_error	aes_shadow_reg_errors	5.000s	442.557us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	5.000s	442.557us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	5.000s	442.557us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	5.000s	442.557us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	5.000s	433.511us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	11.000s	932.753us	5	5	100.00
		aes_tl_intg_err	6.000s	232.738us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	232.738us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	12.000s	242.485us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	5.000s	442.557us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	14.000s	373.598us	50	50	100.00
		aes_stress	3.517m	2.680ms	50	50	100.00
		aes_alert_reset	12.000s	242.485us	50	50	100.00
		aes_core_fi	51.000s	10.005ms	68	70	97.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	5.000s	442.557us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_stress	3.517m	2.680ms	50	50	100.00
		aes_readability	10.000s	940.168us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	3.517m	2.680ms	50	50	100.00
		aes_sideload	11.000s	347.074us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	10.000s	940.168us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	10.000s	940.168us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	10.000s	940.168us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	10.000s	940.168us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	10.000s	940.168us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	3.517m	2.680ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	3.517m	2.680ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	14.000s	697.629us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	14.000s	697.629us	50	50	100.00
		aes_control_fi	47.000s	10.006ms	280	300	93.33
		aes_cipher_fi	45.000s	10.010ms	338	350	96.57
		aes_ctr_fi	12.000s	518.174us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	14.000s	697.629us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	14.000s	697.629us	50	50	100.00
		aes_control_fi	47.000s	10.006ms	280	300	93.33
		aes_cipher_fi	45.000s	10.010ms	338	350	96.57
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	45.000s	10.010ms	338	350	96.57
V2S	sec_cm_ctr_fsm_sparse	aes_fi	14.000s	697.629us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	14.000s	697.629us	50	50	100.00
		aes_control_fi	47.000s	10.006ms	280	300	93.33
		aes_ctr_fi	12.000s	518.174us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	14.000s	697.629us	50	50	100.00
		aes_control_fi	47.000s	10.006ms	280	300	93.33
		aes_cipher_fi	45.000s	10.010ms	338	350	96.57
		aes_ctr_fi	12.000s	518.174us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	12.000s	242.485us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	14.000s	697.629us	50	50	100.00
		aes_control_fi	47.000s	10.006ms	280	300	93.33
		aes_cipher_fi	45.000s	10.010ms	338	350	96.57
		aes_ctr_fi	12.000s	518.174us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	14.000s	697.629us	50	50	100.00
		aes_control_fi	47.000s	10.006ms	280	300	93.33
		aes_cipher_fi	45.000s	10.010ms	338	350	96.57
		aes_ctr_fi	12.000s	518.174us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	14.000s	697.629us	50	50	100.00
		aes_control_fi	47.000s	10.006ms	280	300	93.33
		aes_ctr_fi	12.000s	518.174us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	14.000s	697.629us	50	50	100.00
		aes_control_fi	47.000s	10.006ms	280	300	93.33
		aes_cipher_fi	45.000s	10.010ms	338	350	96.57
V2S		TOTAL			951	985	96.55
V3		TOTAL			0	0	--
		TOTAL			1548	1582	97.85

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	12	12	12	100.00
V2S	11	11	8	72.73

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.48	99.02	97.55	99.42	95.85	95.66	98.52	98.82	92.49

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 20 failures:
- Test aes_cipher_fi has 5 failures.
  - 11.aes_cipher_fi.226691421
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/11.aes_cipher_fi/latest/run.log
```
  Job ID: smart:65cf5621-f138-4cb7-8d6c-7df90c0526f1
```
  - 37.aes_cipher_fi.732908382
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/37.aes_cipher_fi/latest/run.log
```
  Job ID: smart:cc0a078a-4bc6-47b8-882d-8e6d6a6926f8
```
  - ... and 3 more failures.
- Test aes_control_fi has 15 failures.
  - 19.aes_control_fi.1385264670
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/19.aes_control_fi/latest/run.log
```
  Job ID: smart:2ddd5e69-6b7c-42da-8ac8-b57427d23d60
```
  - 36.aes_control_fi.201404478
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/36.aes_control_fi/latest/run.log
```
  Job ID: smart:79043d89-3f61-45d5-9041-91975277e72a
```
  - ... and 13 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 7 failures:

Test aes_cipher_fi has 7 failures.

106.aes_cipher_fi.2899160776
Line 271, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/106.aes_cipher_fi/latest/run.log

  UVM_FATAL @ 10007126647 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007126647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

212.aes_cipher_fi.1045549157
Line 279, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/212.aes_cipher_fi/latest/run.log

  UVM_FATAL @ 10019168623 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10019168623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 5 failures:

Test aes_control_fi has 5 failures.

94.aes_control_fi.813091026
Line 282, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/94.aes_control_fi/latest/run.log

  UVM_FATAL @ 10006321624 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006321624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

109.aes_control_fi.379075220
Line 282, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/109.aes_control_fi/latest/run.log

  UVM_FATAL @ 10012592337 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012592337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:

Test aes_core_fi has 2 failures.

4.aes_core_fi.3903242379
Line 281, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/4.aes_core_fi/latest/run.log

  UVM_FATAL @ 10005057064 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005057064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

37.aes_core_fi.955994040
Line 278, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/37.aes_core_fi/latest/run.log

  UVM_FATAL @ 10007865288 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007865288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---