8c6aecd4d
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | wake_up | aes_wake_up | 15.000s | 115.559us | 1 | 1 | 100.00 |
V1 | smoke | aes_smoke | 31.000s | 67.979us | 50 | 50 | 100.00 |
V1 | csr_hw_reset | aes_csr_hw_reset | 7.000s | 62.551us | 5 | 5 | 100.00 |
V1 | csr_rw | aes_csr_rw | 27.000s | 62.930us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | aes_csr_bit_bash | 14.000s | 333.377us | 5 | 5 | 100.00 |
V1 | csr_aliasing | aes_csr_aliasing | 29.000s | 897.339us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | aes_csr_mem_rw_with_rand_reset | 20.000s | 60.659us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | aes_csr_rw | 27.000s | 62.930us | 20 | 20 | 100.00 |
aes_csr_aliasing | 29.000s | 897.339us | 5 | 5 | 100.00 | ||
V1 | TOTAL | 106 | 106 | 100.00 | |||
V2 | algorithm | aes_smoke | 31.000s | 67.979us | 50 | 50 | 100.00 |
aes_config_error | 35.000s | 1.612ms | 50 | 50 | 100.00 | ||
aes_stress | 35.000s | 138.830us | 50 | 50 | 100.00 | ||
V2 | key_length | aes_smoke | 31.000s | 67.979us | 50 | 50 | 100.00 |
aes_config_error | 35.000s | 1.612ms | 50 | 50 | 100.00 | ||
aes_stress | 35.000s | 138.830us | 50 | 50 | 100.00 | ||
V2 | back2back | aes_stress | 35.000s | 138.830us | 50 | 50 | 100.00 |
aes_b2b | 46.000s | 3.588ms | 50 | 50 | 100.00 | ||
V2 | backpressure | aes_stress | 35.000s | 138.830us | 50 | 50 | 100.00 |
V2 | multi_message | aes_smoke | 31.000s | 67.979us | 50 | 50 | 100.00 |
aes_config_error | 35.000s | 1.612ms | 50 | 50 | 100.00 | ||
aes_stress | 35.000s | 138.830us | 50 | 50 | 100.00 | ||
aes_alert_reset | 21.000s | 1.311ms | 50 | 50 | 100.00 | ||
V2 | failure_test | aes_man_cfg_err | 21.000s | 64.146us | 50 | 50 | 100.00 |
aes_config_error | 35.000s | 1.612ms | 50 | 50 | 100.00 | ||
aes_alert_reset | 21.000s | 1.311ms | 50 | 50 | 100.00 | ||
V2 | trigger_clear_test | aes_clear | 31.000s | 1.316ms | 50 | 50 | 100.00 |
V2 | nist_test_vectors | aes_nist_vectors | 17.000s | 186.078us | 1 | 1 | 100.00 |
V2 | reset_recovery | aes_alert_reset | 21.000s | 1.311ms | 50 | 50 | 100.00 |
V2 | stress | aes_stress | 35.000s | 138.830us | 50 | 50 | 100.00 |
V2 | sideload | aes_stress | 35.000s | 138.830us | 50 | 50 | 100.00 |
aes_sideload | 27.000s | 750.287us | 50 | 50 | 100.00 | ||
V2 | deinitialization | aes_deinit | 28.000s | 2.219ms | 50 | 50 | 100.00 |
V2 | stress_all | aes_stress_all | 3.350m | 7.008ms | 10 | 10 | 100.00 |
V2 | alert_test | aes_alert_test | 26.000s | 73.834us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | aes_tl_errors | 22.000s | 236.801us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | aes_tl_errors | 22.000s | 236.801us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | aes_csr_hw_reset | 7.000s | 62.551us | 5 | 5 | 100.00 |
aes_csr_rw | 27.000s | 62.930us | 20 | 20 | 100.00 | ||
aes_csr_aliasing | 29.000s | 897.339us | 5 | 5 | 100.00 | ||
aes_same_csr_outstanding | 20.000s | 276.918us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | aes_csr_hw_reset | 7.000s | 62.551us | 5 | 5 | 100.00 |
aes_csr_rw | 27.000s | 62.930us | 20 | 20 | 100.00 | ||
aes_csr_aliasing | 29.000s | 897.339us | 5 | 5 | 100.00 | ||
aes_same_csr_outstanding | 20.000s | 276.918us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 501 | 501 | 100.00 | |||
V2S | reseeding | aes_reseed | 1.050m | 2.143ms | 48 | 50 | 96.00 |
V2S | fault_inject | aes_fi | 1.900m | 3.977ms | 49 | 50 | 98.00 |
aes_control_fi | 55.000s | 10.021ms | 280 | 300 | 93.33 | ||
aes_cipher_fi | 57.000s | 10.030ms | 331 | 350 | 94.57 | ||
V2S | shadow_reg_update_error | aes_shadow_reg_errors | 22.000s | 142.537us | 20 | 20 | 100.00 |
V2S | shadow_reg_read_clear_staged_value | aes_shadow_reg_errors | 22.000s | 142.537us | 20 | 20 | 100.00 |
V2S | shadow_reg_storage_error | aes_shadow_reg_errors | 22.000s | 142.537us | 20 | 20 | 100.00 |
V2S | shadowed_reset_glitch | aes_shadow_reg_errors | 22.000s | 142.537us | 20 | 20 | 100.00 |
V2S | shadow_reg_update_error_with_csr_rw | aes_shadow_reg_errors_with_csr_rw | 16.000s | 97.688us | 20 | 20 | 100.00 |
V2S | tl_intg_err | aes_sec_cm | 32.000s | 1.794ms | 5 | 5 | 100.00 |
aes_tl_intg_err | 16.000s | 310.158us | 20 | 20 | 100.00 | ||
V2S | sec_cm_bus_integrity | aes_tl_intg_err | 16.000s | 310.158us | 20 | 20 | 100.00 |
V2S | sec_cm_lc_escalate_en_intersig_mubi | aes_alert_reset | 21.000s | 1.311ms | 50 | 50 | 100.00 |
V2S | sec_cm_main_config_shadow | aes_shadow_reg_errors | 22.000s | 142.537us | 20 | 20 | 100.00 |
V2S | sec_cm_main_config_sparse | aes_smoke | 31.000s | 67.979us | 50 | 50 | 100.00 |
aes_stress | 35.000s | 138.830us | 50 | 50 | 100.00 | ||
aes_alert_reset | 21.000s | 1.311ms | 50 | 50 | 100.00 | ||
aes_core_fi | 3.700m | 10.020ms | 67 | 70 | 95.71 | ||
V2S | sec_cm_aux_config_shadow | aes_shadow_reg_errors | 22.000s | 142.537us | 20 | 20 | 100.00 |
V2S | sec_cm_aux_config_regwen | aes_readability | 19.000s | 94.355us | 50 | 50 | 100.00 |
aes_stress | 35.000s | 138.830us | 50 | 50 | 100.00 | ||
V2S | sec_cm_key_sideload | aes_stress | 35.000s | 138.830us | 50 | 50 | 100.00 |
aes_sideload | 27.000s | 750.287us | 50 | 50 | 100.00 | ||
V2S | sec_cm_key_sw_unreadable | aes_readability | 19.000s | 94.355us | 50 | 50 | 100.00 |
V2S | sec_cm_data_reg_sw_unreadable | aes_readability | 19.000s | 94.355us | 50 | 50 | 100.00 |
V2S | sec_cm_key_sec_wipe | aes_readability | 19.000s | 94.355us | 50 | 50 | 100.00 |
V2S | sec_cm_iv_config_sec_wipe | aes_readability | 19.000s | 94.355us | 50 | 50 | 100.00 |
V2S | sec_cm_data_reg_sec_wipe | aes_readability | 19.000s | 94.355us | 50 | 50 | 100.00 |
V2S | sec_cm_data_reg_key_sca | aes_stress | 35.000s | 138.830us | 50 | 50 | 100.00 |
V2S | sec_cm_key_masking | aes_stress | 35.000s | 138.830us | 50 | 50 | 100.00 |
V2S | sec_cm_main_fsm_sparse | aes_fi | 1.900m | 3.977ms | 49 | 50 | 98.00 |
V2S | sec_cm_main_fsm_redun | aes_fi | 1.900m | 3.977ms | 49 | 50 | 98.00 |
aes_control_fi | 55.000s | 10.021ms | 280 | 300 | 93.33 | ||
aes_cipher_fi | 57.000s | 10.030ms | 331 | 350 | 94.57 | ||
aes_ctr_fi | 22.000s | 71.136us | 49 | 50 | 98.00 | ||
V2S | sec_cm_cipher_fsm_sparse | aes_fi | 1.900m | 3.977ms | 49 | 50 | 98.00 |
V2S | sec_cm_cipher_fsm_redun | aes_fi | 1.900m | 3.977ms | 49 | 50 | 98.00 |
aes_control_fi | 55.000s | 10.021ms | 280 | 300 | 93.33 | ||
aes_cipher_fi | 57.000s | 10.030ms | 331 | 350 | 94.57 | ||
V2S | sec_cm_cipher_ctr_redun | aes_cipher_fi | 57.000s | 10.030ms | 331 | 350 | 94.57 |
V2S | sec_cm_ctr_fsm_sparse | aes_fi | 1.900m | 3.977ms | 49 | 50 | 98.00 |
V2S | sec_cm_ctr_fsm_redun | aes_fi | 1.900m | 3.977ms | 49 | 50 | 98.00 |
aes_control_fi | 55.000s | 10.021ms | 280 | 300 | 93.33 | ||
aes_ctr_fi | 22.000s | 71.136us | 49 | 50 | 98.00 | ||
V2S | sec_cm_ctrl_sparse | aes_fi | 1.900m | 3.977ms | 49 | 50 | 98.00 |
aes_control_fi | 55.000s | 10.021ms | 280 | 300 | 93.33 | ||
aes_cipher_fi | 57.000s | 10.030ms | 331 | 350 | 94.57 | ||
aes_ctr_fi | 22.000s | 71.136us | 49 | 50 | 98.00 | ||
V2S | sec_cm_main_fsm_global_esc | aes_alert_reset | 21.000s | 1.311ms | 50 | 50 | 100.00 |
V2S | sec_cm_main_fsm_local_esc | aes_fi | 1.900m | 3.977ms | 49 | 50 | 98.00 |
aes_control_fi | 55.000s | 10.021ms | 280 | 300 | 93.33 | ||
aes_cipher_fi | 57.000s | 10.030ms | 331 | 350 | 94.57 | ||
aes_ctr_fi | 22.000s | 71.136us | 49 | 50 | 98.00 | ||
V2S | sec_cm_cipher_fsm_local_esc | aes_fi | 1.900m | 3.977ms | 49 | 50 | 98.00 |
aes_control_fi | 55.000s | 10.021ms | 280 | 300 | 93.33 | ||
aes_cipher_fi | 57.000s | 10.030ms | 331 | 350 | 94.57 | ||
aes_ctr_fi | 22.000s | 71.136us | 49 | 50 | 98.00 | ||
V2S | sec_cm_ctr_fsm_local_esc | aes_fi | 1.900m | 3.977ms | 49 | 50 | 98.00 |
aes_control_fi | 55.000s | 10.021ms | 280 | 300 | 93.33 | ||
aes_ctr_fi | 22.000s | 71.136us | 49 | 50 | 98.00 | ||
V2S | sec_cm_data_reg_local_esc | aes_fi | 1.900m | 3.977ms | 49 | 50 | 98.00 |
aes_control_fi | 55.000s | 10.021ms | 280 | 300 | 93.33 | ||
aes_cipher_fi | 57.000s | 10.030ms | 331 | 350 | 94.57 | ||
V2S | TOTAL | 939 | 985 | 95.33 | |||
V3 | stress_all_with_rand_reset | aes_stress_all_with_rand_reset | 2.017m | 4.174ms | 0 | 10 | 0.00 |
V3 | TOTAL | 0 | 10 | 0.00 | |||
TOTAL | 1546 | 1602 | 96.50 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 7 | 7 | 7 | 100.00 |
V2 | 13 | 13 | 13 | 100.00 |
V2S | 11 | 11 | 5 | 45.45 |
V3 | 1 | 1 | 0 | 0.00 |
Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
---|---|---|---|---|---|---|---|---|
98.58 | 99.05 | 97.62 | 99.45 | 95.81 | 95.60 | 100.00 | 99.12 | 98.78 |
Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out
has 23 failures:
Test aes_ctr_fi has 1 failures.
17.aes_ctr_fi.858013091
Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/17.aes_ctr_fi/latest/run.log
Job ID: smart:4bca2016-70d3-418b-bffb-413e29ea537a
Test aes_cipher_fi has 8 failures.
32.aes_cipher_fi.1773078035
Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/32.aes_cipher_fi/latest/run.log
Job ID: smart:8c1a952d-375c-44ed-9047-35738d2d57fc
104.aes_cipher_fi.305195043
Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/104.aes_cipher_fi/latest/run.log
Job ID: smart:09a833ed-b260-4d28-a338-053800a0b6c4
... and 6 more failures.
Test aes_control_fi has 14 failures.
34.aes_control_fi.1498603074
Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/34.aes_control_fi/latest/run.log
Job ID: smart:4d30a429-f714-4014-8cc0-8444ea613c59
123.aes_control_fi.617860964
Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/123.aes_control_fi/latest/run.log
Job ID: smart:e760921b-01cc-4b1f-a950-4702e12627c2
... and 12 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred!
has 11 failures:
34.aes_cipher_fi.1933419561
Line 287, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/34.aes_cipher_fi/latest/run.log
UVM_FATAL @ 10093702889 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10093702889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
184.aes_cipher_fi.4136561258
Line 277, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/184.aes_cipher_fi/latest/run.log
UVM_FATAL @ 10009294482 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10009294482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 9 more failures.
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
has 7 failures:
0.aes_stress_all_with_rand_reset.2500739409
Line 483, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 413601461 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 413601461 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.aes_stress_all_with_rand_reset.2389710372
Line 1320, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2765323023 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 2765323023 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred!
has 6 failures:
51.aes_control_fi.2630328182
Line 284, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/51.aes_control_fi/latest/run.log
UVM_FATAL @ 10015229210 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10015229210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
99.aes_control_fi.754602360
Line 279, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/99.aes_control_fi/latest/run.log
UVM_FATAL @ 10009580164 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10009580164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
has 2 failures:
4.aes_stress_all_with_rand_reset.447971550
Line 805, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1301364679 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 1301364679 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.aes_stress_all_with_rand_reset.375384508
Line 1435, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/8.aes_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 12195576533 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 12195576533 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred!
has 2 failures:
13.aes_core_fi.1757187998
Line 278, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/13.aes_core_fi/latest/run.log
UVM_FATAL @ 10027663919 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
UVM_INFO @ 10027663919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
35.aes_core_fi.1193828517
Line 275, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/35.aes_core_fi/latest/run.log
UVM_FATAL @ 10014973936 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
UVM_INFO @ 10014973936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_reseed_vseq.sv:40) [aes_reseed_vseq] Check failed request_seen | finished_all_msgs == *'b* (* [*] vs * [*])
has 2 failures:
16.aes_reseed.603562557
Line 981, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/16.aes_reseed/latest/run.log
UVM_FATAL @ 164815000 ps: (aes_reseed_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen | finished_all_msgs == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 164815000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
47.aes_reseed.4269462127
Line 749, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/47.aes_reseed/latest/run.log
UVM_FATAL @ 54773142 ps: (aes_reseed_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen | finished_all_msgs == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 54773142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_fi_vseq.sv:69) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset
has 1 failures:
0.aes_fi.4137469641
Line 61720, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_fi/latest/run.log
UVM_FATAL @ 2237904452 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
UVM_INFO @ 2237904452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*) == *
has 1 failures:
2.aes_core_fi.3332812580
Line 273, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_core_fi/latest/run.log
UVM_FATAL @ 10020243890 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0xbfaf84) == 0x0
UVM_INFO @ 10020243890 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:520) [aes_alert_reset_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_fault fired unexpectedly!
has 1 failures:
6.aes_stress_all_with_rand_reset.3342734995
Line 662, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 496048898 ps: (cip_base_vseq.sv:520) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_fault fired unexpectedly!
UVM_INFO @ 496048898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---