AES/UNMASKED Simulation Results

Tuesday May 16 2023 07:02:31 UTC

GitHub Revision: `50278df8b`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 1341560578

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	123.119us	1	1	100.00
V1	smoke	aes_smoke	5.000s	136.267us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	66.646us	5	5	100.00
V1	csr_rw	aes_csr_rw	4.000s	75.718us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	11.000s	2.357ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	168.709us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	333.833us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	75.718us	20	20	100.00
		aes_csr_aliasing	5.000s	168.709us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	5.000s	136.267us	50	50	100.00
		aes_config_error	10.000s	335.433us	50	50	100.00
		aes_stress	35.000s	880.400us	50	50	100.00
V2	key_length	aes_smoke	5.000s	136.267us	50	50	100.00
		aes_config_error	10.000s	335.433us	50	50	100.00
		aes_stress	35.000s	880.400us	50	50	100.00
V2	back2back	aes_stress	35.000s	880.400us	50	50	100.00
		aes_b2b	12.000s	238.619us	50	50	100.00
V2	backpressure	aes_stress	35.000s	880.400us	50	50	100.00
V2	multi_message	aes_smoke	5.000s	136.267us	50	50	100.00
		aes_config_error	10.000s	335.433us	50	50	100.00
		aes_stress	35.000s	880.400us	50	50	100.00
		aes_alert_reset	5.000s	73.201us	50	50	100.00
V2	failure_test	aes_config_error	10.000s	335.433us	50	50	100.00
		aes_alert_reset	5.000s	73.201us	50	50	100.00
		aes_man_cfg_err	5.000s	97.819us	50	50	100.00
V2	trigger_clear_test	aes_clear	7.000s	202.282us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	204.550us	1	1	100.00
V2	reset_recovery	aes_alert_reset	5.000s	73.201us	50	50	100.00
V2	stress	aes_stress	35.000s	880.400us	50	50	100.00
V2	sideload	aes_stress	35.000s	880.400us	50	50	100.00
		aes_sideload	5.000s	105.622us	50	50	100.00
V2	deinitialization	aes_deinit	6.000s	291.685us	50	50	100.00
V2	alert_test	aes_alert_test	4.000s	88.171us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	166.414us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	166.414us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	66.646us	5	5	100.00
		aes_csr_rw	4.000s	75.718us	20	20	100.00
		aes_csr_aliasing	5.000s	168.709us	5	5	100.00
		aes_same_csr_outstanding	5.000s	1.267ms	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	66.646us	5	5	100.00
		aes_csr_rw	4.000s	75.718us	20	20	100.00
		aes_csr_aliasing	5.000s	168.709us	5	5	100.00
		aes_same_csr_outstanding	5.000s	1.267ms	20	20	100.00
V2		TOTAL			491	491	100.00
V2S	reseeding	aes_reseed	42.000s	555.911us	48	50	96.00
V2S	fault_inject	aes_fi	6.000s	95.287us	49	50	98.00
		aes_control_fi	56.000s	63.026ms	272	300	90.67
		aes_cipher_fi	51.000s	65.627ms	325	350	92.86
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	71.978us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	71.978us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	71.978us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	71.978us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	6.000s	1.143ms	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	7.000s	1.590ms	5	5	100.00
		aes_tl_intg_err	5.000s	1.105ms	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	1.105ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	5.000s	73.201us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	71.978us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	5.000s	136.267us	50	50	100.00
		aes_stress	35.000s	880.400us	50	50	100.00
		aes_alert_reset	5.000s	73.201us	50	50	100.00
		aes_core_fi	25.000s	10.004ms	69	70	98.57
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	71.978us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_stress	35.000s	880.400us	50	50	100.00
		aes_readability	5.000s	136.177us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	35.000s	880.400us	50	50	100.00
		aes_sideload	5.000s	105.622us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	5.000s	136.177us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	5.000s	136.177us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	5.000s	136.177us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	5.000s	136.177us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	5.000s	136.177us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	35.000s	880.400us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	35.000s	880.400us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	6.000s	95.287us	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	6.000s	95.287us	49	50	98.00
		aes_control_fi	56.000s	63.026ms	272	300	90.67
		aes_cipher_fi	51.000s	65.627ms	325	350	92.86
		aes_ctr_fi	4.000s	73.124us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	6.000s	95.287us	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	6.000s	95.287us	49	50	98.00
		aes_control_fi	56.000s	63.026ms	272	300	90.67
		aes_cipher_fi	51.000s	65.627ms	325	350	92.86
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	51.000s	65.627ms	325	350	92.86
V2S	sec_cm_ctr_fsm_sparse	aes_fi	6.000s	95.287us	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	6.000s	95.287us	49	50	98.00
		aes_control_fi	56.000s	63.026ms	272	300	90.67
		aes_ctr_fi	4.000s	73.124us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	6.000s	95.287us	49	50	98.00
		aes_control_fi	56.000s	63.026ms	272	300	90.67
		aes_cipher_fi	51.000s	65.627ms	325	350	92.86
		aes_ctr_fi	4.000s	73.124us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	5.000s	73.201us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	6.000s	95.287us	49	50	98.00
		aes_control_fi	56.000s	63.026ms	272	300	90.67
		aes_cipher_fi	51.000s	65.627ms	325	350	92.86
		aes_ctr_fi	4.000s	73.124us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	6.000s	95.287us	49	50	98.00
		aes_control_fi	56.000s	63.026ms	272	300	90.67
		aes_cipher_fi	51.000s	65.627ms	325	350	92.86
		aes_ctr_fi	4.000s	73.124us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	6.000s	95.287us	49	50	98.00
		aes_control_fi	56.000s	63.026ms	272	300	90.67
		aes_ctr_fi	4.000s	73.124us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	6.000s	95.287us	49	50	98.00
		aes_control_fi	56.000s	63.026ms	272	300	90.67
		aes_cipher_fi	51.000s	65.627ms	325	350	92.86
V2S		TOTAL			928	985	94.21
V3		TOTAL			0	0	--
		TOTAL			1525	1582	96.40

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	12	12	12	100.00
V2S	11	11	6	54.55

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.13	97.56	94.48	98.79	93.63	97.72	91.11	98.07	92.90

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 32 failures:
- Test aes_cipher_fi has 17 failures.
  - 5.aes_cipher_fi.291750187
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/5.aes_cipher_fi/latest/run.log
```
  Job ID: smart:e3338df4-2c16-4620-9af2-20173d9fecfd
```
  - 25.aes_cipher_fi.2754425551
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/25.aes_cipher_fi/latest/run.log
```
  Job ID: smart:c6240373-2bf5-4a53-bbcd-1cda0fbbfd5b
```
  - ... and 15 more failures.
- Test aes_control_fi has 15 failures.
  - 19.aes_control_fi.751615103
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/19.aes_control_fi/latest/run.log
```
  Job ID: smart:75a84326-ebe2-4b3a-aad7-a0bb9b41bba2
```
  - 20.aes_control_fi.1781697959
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/20.aes_control_fi/latest/run.log
```
  Job ID: smart:10c9c00f-6759-47a9-8361-7ee94780ab92
```
  - ... and 13 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 13 failures:

Test aes_control_fi has 13 failures.

3.aes_control_fi.1304064174
Line 267, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_control_fi/latest/run.log

  UVM_FATAL @ 10004782427 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004782427 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

26.aes_control_fi.2104252611
Line 275, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/26.aes_control_fi/latest/run.log

  UVM_FATAL @ 10009060828 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009060828 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 11 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 8 failures:

Test aes_cipher_fi has 8 failures.

13.aes_cipher_fi.3620655905
Line 272, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/13.aes_cipher_fi/latest/run.log

  UVM_FATAL @ 10008966394 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008966394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

70.aes_cipher_fi.2677886676
Line 273, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/70.aes_cipher_fi/latest/run.log

  UVM_FATAL @ 10045027415 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10045027415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_FATAL (aes_scoreboard.sv:621) scoreboard [scoreboard] # * has 2 failures:

Test aes_reseed has 2 failures.

38.aes_reseed.1974388833
Line 2993, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/38.aes_reseed/latest/run.log

  UVM_FATAL @  13409043 ps: (aes_scoreboard.sv:621) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]  # 0
            TEST FAILED MESSAGES DID NOT MATCH
  
                 0 01      82      40      0
                 1 00      6c      de      0

49.aes_reseed.351302896
Line 4516, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/49.aes_reseed/latest/run.log

  UVM_FATAL @  18697350 ps: (aes_scoreboard.sv:621) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]  # 0
            TEST FAILED MESSAGES DID NOT MATCH
  
                 0 f3      79      2c      0
                 1 00      d4      26      0

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,978): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:

Test aes_fi has 1 failures.

2.aes_fi.3050210724
Line 1970, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_fi/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,978): (time 31496280 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 31456280 PS)
  UVM_ERROR @  31496280 ps: (aes_core.sv:978) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @  31496280 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 51.aes_core_fi.4115241009
    Line 272, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/51.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10003907623 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003907623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```