AES/UNMASKED Simulation Results

Thursday July 25 2024 23:02:35 UTC

GitHub Revision: `a47820eb4c`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 42717125255024305080795900498886328747526075712606813106869971419713539568742

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	63.501us	1	1	100.00
V1	smoke	aes_smoke	14.000s	98.296us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	83.914us	5	5	100.00
V1	csr_rw	aes_csr_rw	7.000s	69.792us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	9.000s	789.101us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	539.725us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	13.000s	184.613us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	7.000s	69.792us	20	20	100.00
		aes_csr_aliasing	5.000s	539.725us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	14.000s	98.296us	50	50	100.00
		aes_config_error	13.000s	57.326us	50	50	100.00
		aes_stress	18.000s	129.549us	50	50	100.00
V2	key_length	aes_smoke	14.000s	98.296us	50	50	100.00
		aes_config_error	13.000s	57.326us	50	50	100.00
		aes_stress	18.000s	129.549us	50	50	100.00
V2	back2back	aes_stress	18.000s	129.549us	50	50	100.00
		aes_b2b	18.000s	549.166us	50	50	100.00
V2	backpressure	aes_stress	18.000s	129.549us	50	50	100.00
V2	multi_message	aes_smoke	14.000s	98.296us	50	50	100.00
		aes_config_error	13.000s	57.326us	50	50	100.00
		aes_stress	18.000s	129.549us	50	50	100.00
		aes_alert_reset	13.000s	95.864us	50	50	100.00
V2	failure_test	aes_man_cfg_err	13.000s	58.401us	50	50	100.00
		aes_config_error	13.000s	57.326us	50	50	100.00
		aes_alert_reset	13.000s	95.864us	50	50	100.00
V2	trigger_clear_test	aes_clear	14.000s	148.816us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	157.857us	1	1	100.00
V2	reset_recovery	aes_alert_reset	13.000s	95.864us	50	50	100.00
V2	stress	aes_stress	18.000s	129.549us	50	50	100.00
V2	sideload	aes_stress	18.000s	129.549us	50	50	100.00
		aes_sideload	14.000s	278.628us	50	50	100.00
V2	deinitialization	aes_deinit	14.000s	125.633us	50	50	100.00
V2	stress_all	aes_stress_all	27.000s	2.194ms	10	10	100.00
V2	alert_test	aes_alert_test	8.000s	53.715us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	15.000s	469.384us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	15.000s	469.384us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	83.914us	5	5	100.00
		aes_csr_rw	7.000s	69.792us	20	20	100.00
		aes_csr_aliasing	5.000s	539.725us	5	5	100.00
		aes_same_csr_outstanding	13.000s	84.404us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	83.914us	5	5	100.00
		aes_csr_rw	7.000s	69.792us	20	20	100.00
		aes_csr_aliasing	5.000s	539.725us	5	5	100.00
		aes_same_csr_outstanding	13.000s	84.404us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	13.000s	82.787us	50	50	100.00
V2S	fault_inject	aes_fi	14.000s	162.274us	49	50	98.00
		aes_control_fi	46.000s	10.002ms	268	300	89.33
		aes_cipher_fi	53.000s	40.413ms	324	350	92.57
V2S	shadow_reg_update_error	aes_shadow_reg_errors	8.000s	61.974us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	8.000s	61.974us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	8.000s	61.974us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	8.000s	61.974us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	8.000s	212.541us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	10.000s	1.949ms	5	5	100.00
		aes_tl_intg_err	9.000s	451.858us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	9.000s	451.858us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	13.000s	95.864us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	8.000s	61.974us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	14.000s	98.296us	50	50	100.00
		aes_stress	18.000s	129.549us	50	50	100.00
		aes_alert_reset	13.000s	95.864us	50	50	100.00
		aes_core_fi	22.000s	10.013ms	69	70	98.57
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	8.000s	61.974us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	13.000s	86.216us	50	50	100.00
		aes_stress	18.000s	129.549us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	18.000s	129.549us	50	50	100.00
		aes_sideload	14.000s	278.628us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	13.000s	86.216us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	13.000s	86.216us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	13.000s	86.216us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	13.000s	86.216us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	13.000s	86.216us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	18.000s	129.549us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	18.000s	129.549us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	14.000s	162.274us	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	14.000s	162.274us	49	50	98.00
		aes_control_fi	46.000s	10.002ms	268	300	89.33
		aes_cipher_fi	53.000s	40.413ms	324	350	92.57
		aes_ctr_fi	15.000s	168.103us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	14.000s	162.274us	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	14.000s	162.274us	49	50	98.00
		aes_control_fi	46.000s	10.002ms	268	300	89.33
		aes_cipher_fi	53.000s	40.413ms	324	350	92.57
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	53.000s	40.413ms	324	350	92.57
V2S	sec_cm_ctr_fsm_sparse	aes_fi	14.000s	162.274us	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	14.000s	162.274us	49	50	98.00
		aes_control_fi	46.000s	10.002ms	268	300	89.33
		aes_ctr_fi	15.000s	168.103us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	14.000s	162.274us	49	50	98.00
		aes_control_fi	46.000s	10.002ms	268	300	89.33
		aes_cipher_fi	53.000s	40.413ms	324	350	92.57
		aes_ctr_fi	15.000s	168.103us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	13.000s	95.864us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	14.000s	162.274us	49	50	98.00
		aes_control_fi	46.000s	10.002ms	268	300	89.33
		aes_cipher_fi	53.000s	40.413ms	324	350	92.57
		aes_ctr_fi	15.000s	168.103us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	14.000s	162.274us	49	50	98.00
		aes_control_fi	46.000s	10.002ms	268	300	89.33
		aes_cipher_fi	53.000s	40.413ms	324	350	92.57
		aes_ctr_fi	15.000s	168.103us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	14.000s	162.274us	49	50	98.00
		aes_control_fi	46.000s	10.002ms	268	300	89.33
		aes_ctr_fi	15.000s	168.103us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	14.000s	162.274us	49	50	98.00
		aes_control_fi	46.000s	10.002ms	268	300	89.33
		aes_cipher_fi	53.000s	40.413ms	324	350	92.57
V2S		TOTAL			925	985	93.91
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	2.283m	18.677ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1532	1602	95.63

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.06	97.41	94.22	98.66	93.42	97.72	91.11	98.66	96.41

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 34 failures:
- Test aes_cipher_fi has 17 failures.
  - 16.aes_cipher_fi.30875586005045413409411409828430828988622028401346889573424549484830413470499
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/16.aes_cipher_fi/latest/run.log
```
  Job ID: smart:ec5ec052-bc69-40d8-8a75-c1305496913d
```
  - 22.aes_cipher_fi.36292997213094165336337955215816469725175217586870563653086945953266140876418
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/22.aes_cipher_fi/latest/run.log
```
  Job ID: smart:e3219889-c25e-4615-b2b9-39535a6a2db7
```
  - ... and 15 more failures.
- Test aes_control_fi has 17 failures.
  - 21.aes_control_fi.41448010509384137139229922594072552315205224553254233385691574555019515925910
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/21.aes_control_fi/latest/run.log
```
  Job ID: smart:a2c0ce21-3429-4c7a-b98d-d6adf05b57eb
```
  - 44.aes_control_fi.11663586092738871097143013621129504223283211854995721030405694682554218780831
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/44.aes_control_fi/latest/run.log
```
  Job ID: smart:ebb86467-12e8-4d20-bd64-ca6198cc2a51
```
  - ... and 15 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 15 failures:
- Test aes_control_fi has 15 failures.
  - 36.aes_control_fi.93979162826950506383129812232456163985115651239525866283980842807492816903213
    Line 332, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/36.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10005652992 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005652992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 43.aes_control_fi.67691457180971000363171465087701375388680976633809910530180800669698781540365
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/43.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10003477626 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003477626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 13 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_cipher_fi has 9 failures.
  - 96.aes_cipher_fi.81909735315437284745008070722637819366098497749898977534553270470397014837240
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/96.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10002483747 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002483747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 119.aes_cipher_fi.88409435865712114563824848799140164232209842513044172865194019104344914835867
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/119.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10007158339 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007158339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

1.aes_stress_all_with_rand_reset.108186252829248883363415839436670773351089915100653342009261194881180922406178
Line 750, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1889217676 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1889217676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.34244505724735605113547845097918314168621808375197968382483804529117863745958
Line 1127, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3230047275 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3230047275 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 4 failures:

Test aes_stress_all_with_rand_reset has 4 failures.

0.aes_stress_all_with_rand_reset.89981086518607606646833544275473568418263114530871433142797581785942009630475
Line 781, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 161380845 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 161380845 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.7584087072631346248522030067742302488459906357628301066320729446672882401113
Line 683, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 645131145 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 645131145 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 14.aes_core_fi.4629970176973630697770454066563141303948639889223439877502606075152806241972
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/14.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10012546103 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012546103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_fi_vseq.sv:69) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset has 1 failures:
- Test aes_fi has 1 failures.
  - 20.aes_fi.56798387570931173529485799510344173915795261085800759257232989927291559370376
    Line 4399, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/20.aes_fi/latest/run.log
```
  UVM_FATAL @  29892142 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @  29892142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```