AES/UNMASKED Simulation Results

Monday October 14 2024 17:26:15 UTC

GitHub Revision: `12e3b8572e`

Branch: os_regression_2024_10_14

Simulator: XCELIUM

Build randomization enabled with --build-seed 85025606402499621082521464627961092918263397067038954055071960501195381950243

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	247.271us	1	1	100.00
V1	smoke	aes_smoke	1.883m	64.982us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	27.000s	60.022us	5	5	100.00
V1	csr_rw	aes_csr_rw	1.300m	201.613us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	30.000s	616.577us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	26.000s	95.581us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	1.317m	108.661us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	1.300m	201.613us	20	20	100.00
		aes_csr_aliasing	26.000s	95.581us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	1.883m	64.982us	50	50	100.00
		aes_config_error	1.767m	108.695us	50	50	100.00
		aes_stress	1.950m	90.087us	50	50	100.00
V2	key_length	aes_smoke	1.883m	64.982us	50	50	100.00
		aes_config_error	1.767m	108.695us	50	50	100.00
		aes_stress	1.950m	90.087us	50	50	100.00
V2	back2back	aes_stress	1.950m	90.087us	50	50	100.00
		aes_b2b	1.933m	192.045us	50	50	100.00
V2	backpressure	aes_stress	1.950m	90.087us	50	50	100.00
V2	multi_message	aes_smoke	1.883m	64.982us	50	50	100.00
		aes_config_error	1.767m	108.695us	50	50	100.00
		aes_stress	1.950m	90.087us	50	50	100.00
		aes_alert_reset	1.867m	66.567us	50	50	100.00
V2	failure_test	aes_man_cfg_err	1.700m	102.678us	50	50	100.00
		aes_config_error	1.767m	108.695us	50	50	100.00
		aes_alert_reset	1.867m	66.567us	50	50	100.00
V2	trigger_clear_test	aes_clear	1.867m	202.302us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	8.000s	153.185us	1	1	100.00
V2	reset_recovery	aes_alert_reset	1.867m	66.567us	50	50	100.00
V2	stress	aes_stress	1.950m	90.087us	50	50	100.00
V2	sideload	aes_stress	1.950m	90.087us	50	50	100.00
		aes_sideload	1.667m	101.418us	50	50	100.00
V2	deinitialization	aes_deinit	1.767m	84.164us	50	50	100.00
V2	stress_all	aes_stress_all	24.000s	775.665us	10	10	100.00
V2	alert_test	aes_alert_test	1.883m	62.797us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	1.533m	80.854us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	1.533m	80.854us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	27.000s	60.022us	5	5	100.00
		aes_csr_rw	1.300m	201.613us	20	20	100.00
		aes_csr_aliasing	26.000s	95.581us	5	5	100.00
		aes_same_csr_outstanding	1.400m	71.345us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	27.000s	60.022us	5	5	100.00
		aes_csr_rw	1.300m	201.613us	20	20	100.00
		aes_csr_aliasing	26.000s	95.581us	5	5	100.00
		aes_same_csr_outstanding	1.400m	71.345us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	1.817m	145.626us	50	50	100.00
V2S	fault_inject	aes_fi	2.033m	77.925us	49	50	98.00
		aes_control_fi	1.317m	54.693us	235	300	78.33
		aes_cipher_fi	1.200m	137.616us	287	350	82.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	1.867m	81.224us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	1.867m	81.224us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	1.867m	81.224us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	1.867m	81.224us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	1.350m	120.900us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	7.000s	421.704us	5	5	100.00
		aes_tl_intg_err	1.517m	4.048ms	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	1.517m	4.048ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	1.867m	66.567us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	1.867m	81.224us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	1.883m	64.982us	50	50	100.00
		aes_stress	1.950m	90.087us	50	50	100.00
		aes_alert_reset	1.867m	66.567us	50	50	100.00
		aes_core_fi	1.867m	70.806us	69	70	98.57
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	1.867m	81.224us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	1.933m	50.647us	50	50	100.00
		aes_stress	1.950m	90.087us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	1.950m	90.087us	50	50	100.00
		aes_sideload	1.667m	101.418us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	1.933m	50.647us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	1.933m	50.647us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	1.933m	50.647us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	1.933m	50.647us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	1.933m	50.647us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	1.950m	90.087us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	1.950m	90.087us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	2.033m	77.925us	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	2.033m	77.925us	49	50	98.00
		aes_control_fi	1.317m	54.693us	235	300	78.33
		aes_cipher_fi	1.200m	137.616us	287	350	82.00
		aes_ctr_fi	1.133m	50.457us	40	50	80.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	2.033m	77.925us	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	2.033m	77.925us	49	50	98.00
		aes_control_fi	1.317m	54.693us	235	300	78.33
		aes_cipher_fi	1.200m	137.616us	287	350	82.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	1.200m	137.616us	287	350	82.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	2.033m	77.925us	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	2.033m	77.925us	49	50	98.00
		aes_control_fi	1.317m	54.693us	235	300	78.33
		aes_ctr_fi	1.133m	50.457us	40	50	80.00
V2S	sec_cm_ctrl_sparse	aes_fi	2.033m	77.925us	49	50	98.00
		aes_control_fi	1.317m	54.693us	235	300	78.33
		aes_cipher_fi	1.200m	137.616us	287	350	82.00
		aes_ctr_fi	1.133m	50.457us	40	50	80.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	1.867m	66.567us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	2.033m	77.925us	49	50	98.00
		aes_control_fi	1.317m	54.693us	235	300	78.33
		aes_cipher_fi	1.200m	137.616us	287	350	82.00
		aes_ctr_fi	1.133m	50.457us	40	50	80.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	2.033m	77.925us	49	50	98.00
		aes_control_fi	1.317m	54.693us	235	300	78.33
		aes_cipher_fi	1.200m	137.616us	287	350	82.00
		aes_ctr_fi	1.133m	50.457us	40	50	80.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	2.033m	77.925us	49	50	98.00
		aes_control_fi	1.317m	54.693us	235	300	78.33
		aes_ctr_fi	1.133m	50.457us	40	50	80.00
V2S	sec_cm_data_reg_local_esc	aes_fi	2.033m	77.925us	49	50	98.00
		aes_control_fi	1.317m	54.693us	235	300	78.33
		aes_cipher_fi	1.200m	137.616us	287	350	82.00
V2S		TOTAL			845	985	85.79
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	23.000s	1.746ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1452	1602	90.64

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	6	54.55
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.19	97.50	94.35	98.75	93.65	97.72	91.11	98.85	97.60

Failure Buckets

Job timed out after * minutes has 119 failures:
- Test aes_control_fi has 56 failures.
  - 19.aes_control_fi.73611220460096428106748002244800501104356533633818545333114320127892975674421
    Log /workspaces/repo/scratch/os_regression_2024_10_14/aes_unmasked-sim-xcelium/19.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 21.aes_control_fi.48029467616025886115469026669947866596001318700587608412508604737048015874257
    Log /workspaces/repo/scratch/os_regression_2024_10_14/aes_unmasked-sim-xcelium/21.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 54 more failures.
- Test aes_cipher_fi has 53 failures.
  - 19.aes_cipher_fi.96262372248312027641836184110276815591870669199319692161332609500258024025098
    Log /workspaces/repo/scratch/os_regression_2024_10_14/aes_unmasked-sim-xcelium/19.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 20.aes_cipher_fi.44264617812400370851595544905118335165534383680619877731811258782235375403707
    Log /workspaces/repo/scratch/os_regression_2024_10_14/aes_unmasked-sim-xcelium/20.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 51 more failures.
- Test aes_ctr_fi has 10 failures.
  - 19.aes_ctr_fi.104195121936322762102747841023464861478590869662855066544061487326485594430429
    Log /workspaces/repo/scratch/os_regression_2024_10_14/aes_unmasked-sim-xcelium/19.aes_ctr_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 23.aes_ctr_fi.61551973157316124298121676576944241042623074596534966407375223134156204171130
    Log /workspaces/repo/scratch/os_regression_2024_10_14/aes_unmasked-sim-xcelium/23.aes_ctr_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 8 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 10 failures:
- Test aes_cipher_fi has 10 failures.
  - 11.aes_cipher_fi.79077089470744304127835595712877967166361205544895752091471798194599017359172
    Line 132, in log /workspaces/repo/scratch/os_regression_2024_10_14/aes_unmasked-sim-xcelium/11.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10004137682 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004137682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 56.aes_cipher_fi.41626723990248236446703220355119810992648796208373097043935739235905175376340
    Line 140, in log /workspaces/repo/scratch/os_regression_2024_10_14/aes_unmasked-sim-xcelium/56.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10005600250 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005600250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_control_fi has 9 failures.
  - 45.aes_control_fi.85087253934286687812289303211199998187118593346111812333997169246182805900242
    Line 127, in log /workspaces/repo/scratch/os_regression_2024_10_14/aes_unmasked-sim-xcelium/45.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10003013713 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003013713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 63.aes_control_fi.74811575666296792169549857730084409907434421648083846096851105074877052901985
    Line 128, in log /workspaces/repo/scratch/os_regression_2024_10_14/aes_unmasked-sim-xcelium/63.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10013652932 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013652932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

2.aes_stress_all_with_rand_reset.66953632110232137374902643532446625375722561272936152777247364544970588444640
Line 958, in log /workspaces/repo/scratch/os_regression_2024_10_14/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2265933633 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2265933633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.90348370760054731993870936839240108116791669623728990475116051343204461660005
Line 878, in log /workspaces/repo/scratch/os_regression_2024_10_14/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3155374479 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3155374479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 0.aes_stress_all_with_rand_reset.40295242554428589989028324105831067009567137258088623115182293508537607814813
    Line 876, in log /workspaces/repo/scratch/os_regression_2024_10_14/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 712502416 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 712502416 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 1.aes_stress_all_with_rand_reset.2974132561744520455655023644129776040371694779275495796619995213157304306796
    Line 132, in log /workspaces/repo/scratch/os_regression_2024_10_14/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  69192578 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  69192578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:868) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 7.aes_stress_all_with_rand_reset.54778482642875868368026731390508263600296510799302247874810262161144539157048
    Line 243, in log /workspaces/repo/scratch/os_regression_2024_10_14/aes_unmasked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1006000720 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1006000720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_*_*_*/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:

Test aes_fi has 1 failures.

23.aes_fi.59933134129988779911036766583584944947639692670112292411886077949860694610187
Line 2727, in log /workspaces/repo/scratch/os_regression_2024_10_14/aes_unmasked-sim-xcelium/23.aes_fi/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_10_14/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 11308394 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 11293009 PS)
  UVM_ERROR @  11308394 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @  11308394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 65.aes_core_fi.112281912597938418775914513786364524742546302821554904381093125223582067386694
    Line 143, in log /workspaces/repo/scratch/os_regression_2024_10_14/aes_unmasked-sim-xcelium/65.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10001980520 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10001980520 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```