AES/UNMASKED Simulation Results

Tuesday May 30 2023 07:03:17 UTC

GitHub Revision: `f8b3c19a2`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 1284268927

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	56.058us	1	1	100.00
V1	smoke	aes_smoke	5.000s	92.777us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	63.386us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	66.576us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	726.178us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	226.134us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	3.000s	59.604us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	66.576us	20	20	100.00
		aes_csr_aliasing	5.000s	226.134us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	5.000s	92.777us	50	50	100.00
		aes_config_error	10.000s	474.143us	50	50	100.00
		aes_stress	31.000s	1.698ms	50	50	100.00
V2	key_length	aes_smoke	5.000s	92.777us	50	50	100.00
		aes_config_error	10.000s	474.143us	50	50	100.00
		aes_stress	31.000s	1.698ms	50	50	100.00
V2	back2back	aes_stress	31.000s	1.698ms	50	50	100.00
		aes_b2b	11.000s	127.771us	50	50	100.00
V2	backpressure	aes_stress	31.000s	1.698ms	50	50	100.00
V2	multi_message	aes_smoke	5.000s	92.777us	50	50	100.00
		aes_config_error	10.000s	474.143us	50	50	100.00
		aes_stress	31.000s	1.698ms	50	50	100.00
		aes_alert_reset	6.000s	149.729us	50	50	100.00
V2	failure_test	aes_config_error	10.000s	474.143us	50	50	100.00
		aes_alert_reset	6.000s	149.729us	50	50	100.00
		aes_man_cfg_err	4.000s	56.152us	50	50	100.00
V2	trigger_clear_test	aes_clear	6.000s	126.932us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	158.409us	1	1	100.00
V2	reset_recovery	aes_alert_reset	6.000s	149.729us	50	50	100.00
V2	stress	aes_stress	31.000s	1.698ms	50	50	100.00
V2	sideload	aes_stress	31.000s	1.698ms	50	50	100.00
		aes_sideload	5.000s	86.396us	50	50	100.00
V2	deinitialization	aes_deinit	6.000s	64.797us	50	50	100.00
V2	alert_test	aes_alert_test	4.000s	192.409us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	153.463us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	153.463us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	63.386us	5	5	100.00
		aes_csr_rw	3.000s	66.576us	20	20	100.00
		aes_csr_aliasing	5.000s	226.134us	5	5	100.00
		aes_same_csr_outstanding	4.000s	98.283us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	63.386us	5	5	100.00
		aes_csr_rw	3.000s	66.576us	20	20	100.00
		aes_csr_aliasing	5.000s	226.134us	5	5	100.00
		aes_same_csr_outstanding	4.000s	98.283us	20	20	100.00
V2		TOTAL			491	491	100.00
V2S	reseeding	aes_reseed	43.000s	2.292ms	49	50	98.00
V2S	fault_inject	aes_fi	6.000s	152.999us	50	50	100.00
		aes_control_fi	51.000s	65.635ms	279	300	93.00
		aes_cipher_fi	46.000s	10.008ms	326	350	93.14
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	71.352us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	71.352us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	71.352us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	71.352us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	5.000s	140.085us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	14.000s	3.241ms	5	5	100.00
		aes_tl_intg_err	5.000s	264.334us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	264.334us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	6.000s	149.729us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	71.352us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	5.000s	92.777us	50	50	100.00
		aes_stress	31.000s	1.698ms	50	50	100.00
		aes_alert_reset	6.000s	149.729us	50	50	100.00
		aes_core_fi	1.333m	10.041ms	68	70	97.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	71.352us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_stress	31.000s	1.698ms	50	50	100.00
		aes_readability	4.000s	74.692us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	31.000s	1.698ms	50	50	100.00
		aes_sideload	5.000s	86.396us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	4.000s	74.692us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	4.000s	74.692us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	4.000s	74.692us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	4.000s	74.692us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	4.000s	74.692us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	31.000s	1.698ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	31.000s	1.698ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	6.000s	152.999us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	6.000s	152.999us	50	50	100.00
		aes_control_fi	51.000s	65.635ms	279	300	93.00
		aes_cipher_fi	46.000s	10.008ms	326	350	93.14
		aes_ctr_fi	4.000s	114.374us	49	50	98.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	6.000s	152.999us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	6.000s	152.999us	50	50	100.00
		aes_control_fi	51.000s	65.635ms	279	300	93.00
		aes_cipher_fi	46.000s	10.008ms	326	350	93.14
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	46.000s	10.008ms	326	350	93.14
V2S	sec_cm_ctr_fsm_sparse	aes_fi	6.000s	152.999us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	6.000s	152.999us	50	50	100.00
		aes_control_fi	51.000s	65.635ms	279	300	93.00
		aes_ctr_fi	4.000s	114.374us	49	50	98.00
V2S	sec_cm_ctrl_sparse	aes_fi	6.000s	152.999us	50	50	100.00
		aes_control_fi	51.000s	65.635ms	279	300	93.00
		aes_cipher_fi	46.000s	10.008ms	326	350	93.14
		aes_ctr_fi	4.000s	114.374us	49	50	98.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	6.000s	149.729us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	6.000s	152.999us	50	50	100.00
		aes_control_fi	51.000s	65.635ms	279	300	93.00
		aes_cipher_fi	46.000s	10.008ms	326	350	93.14
		aes_ctr_fi	4.000s	114.374us	49	50	98.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	6.000s	152.999us	50	50	100.00
		aes_control_fi	51.000s	65.635ms	279	300	93.00
		aes_cipher_fi	46.000s	10.008ms	326	350	93.14
		aes_ctr_fi	4.000s	114.374us	49	50	98.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	6.000s	152.999us	50	50	100.00
		aes_control_fi	51.000s	65.635ms	279	300	93.00
		aes_ctr_fi	4.000s	114.374us	49	50	98.00
V2S	sec_cm_data_reg_local_esc	aes_fi	6.000s	152.999us	50	50	100.00
		aes_control_fi	51.000s	65.635ms	279	300	93.00
		aes_cipher_fi	46.000s	10.008ms	326	350	93.14
V2S		TOTAL			936	985	95.03
V3		TOTAL			0	0	--
		TOTAL			1533	1582	96.90

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	12	12	12	100.00
V2S	11	11	6	54.55

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.12	97.60	94.69	98.68	93.74	97.72	91.11	98.07	92.49

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 30 failures:
- Test aes_control_fi has 11 failures.
  - 3.aes_control_fi.428992676
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_control_fi/latest/run.log
```
  Job ID: smart:f2c7301e-1294-4a57-a05b-bc5b7dea5f9b
```
  - 39.aes_control_fi.434780295
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/39.aes_control_fi/latest/run.log
```
  Job ID: smart:c633062e-bb8b-4df9-9106-d5cbfb09dac8
```
  - ... and 9 more failures.
- Test aes_cipher_fi has 18 failures.
  - 12.aes_cipher_fi.3041745154
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/12.aes_cipher_fi/latest/run.log
```
  Job ID: smart:5a09165c-5e66-4084-826e-60d36ba1548f
```
  - 17.aes_cipher_fi.646923583
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/17.aes_cipher_fi/latest/run.log
```
  Job ID: smart:f2ec9b4c-1ad3-472e-ac77-812c82be3ea3
```
  - ... and 16 more failures.
- Test aes_ctr_fi has 1 failures.
  - 19.aes_ctr_fi.821451085
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/19.aes_ctr_fi/latest/run.log
```
  Job ID: smart:9e7f2807-97a8-4699-bc48-93e2006e2c62
```

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 10 failures:

Test aes_control_fi has 10 failures.

2.aes_control_fi.604175323
Line 271, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_control_fi/latest/run.log

  UVM_FATAL @ 10004363861 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004363861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

14.aes_control_fi.2345115686
Line 276, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/14.aes_control_fi/latest/run.log

  UVM_FATAL @ 10002254925 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002254925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 6 failures:

Test aes_cipher_fi has 6 failures.

38.aes_cipher_fi.2577947446
Line 269, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/38.aes_cipher_fi/latest/run.log

  UVM_FATAL @ 10026411722 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10026411722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

45.aes_cipher_fi.1705898843
Line 269, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/45.aes_cipher_fi/latest/run.log

  UVM_FATAL @ 10008103842 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008103842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (aes_scoreboard.sv:621) scoreboard [scoreboard] # * has 1 failures:

Test aes_reseed has 1 failures.

16.aes_reseed.1378083392
Line 1090, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/16.aes_reseed/latest/run.log

  UVM_FATAL @   7806322 ps: (aes_scoreboard.sv:621) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]  # 0
            TEST FAILED MESSAGES DID NOT MATCH
  
                 0 eb      ab      5a      0
                 1 00      59      70      0

UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 16.aes_core_fi.2304022566
    Line 274, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/16.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10027557714 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10027557714 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*) == * has 1 failures:
- Test aes_core_fi has 1 failures.
  - 62.aes_core_fi.1007033824
    Line 268, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/62.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10041363180 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x36c1ea84) == 0x0
  UVM_INFO @ 10041363180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```