AES/UNMASKED Simulation Results

Wednesday November 22 2023 20:02:38 UTC

GitHub Revision: 4002b28ec4

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 56541452733628775295814943325285397402671097056517970046183331126493552547969

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	91.986us	1	1	100.00
V1	smoke	aes_smoke	11.000s	94.633us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	2.000s	68.230us	5	5	100.00
V1	csr_rw	aes_csr_rw	4.000s	65.112us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	7.000s	656.547us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	4.000s	188.636us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	3.000s	67.213us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	65.112us	20	20	100.00
		aes_csr_aliasing	4.000s	188.636us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	11.000s	94.633us	50	50	100.00
		aes_config_error	11.000s	147.222us	50	50	100.00
		aes_stress	11.000s	96.111us	50	50	100.00
V2	key_length	aes_smoke	11.000s	94.633us	50	50	100.00
		aes_config_error	11.000s	147.222us	50	50	100.00
		aes_stress	11.000s	96.111us	50	50	100.00
V2	back2back	aes_stress	11.000s	96.111us	50	50	100.00
		aes_b2b	20.000s	194.836us	50	50	100.00
V2	backpressure	aes_stress	11.000s	96.111us	50	50	100.00
V2	multi_message	aes_smoke	11.000s	94.633us	50	50	100.00
		aes_config_error	11.000s	147.222us	50	50	100.00
		aes_stress	11.000s	96.111us	50	50	100.00
		aes_alert_reset	15.000s	173.633us	50	50	100.00
V2	failure_test	aes_man_cfg_err	13.000s	88.633us	50	50	100.00
		aes_config_error	11.000s	147.222us	50	50	100.00
		aes_alert_reset	15.000s	173.633us	50	50	100.00
V2	trigger_clear_test	aes_clear	14.000s	125.104us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	441.459us	1	1	100.00
V2	reset_recovery	aes_alert_reset	15.000s	173.633us	50	50	100.00
V2	stress	aes_stress	11.000s	96.111us	50	50	100.00
V2	sideload	aes_stress	11.000s	96.111us	50	50	100.00
		aes_sideload	15.000s	101.692us	50	50	100.00
V2	deinitialization	aes_deinit	17.000s	114.339us	50	50	100.00
V2	stress_all	aes_stress_all	11.000s	626.123us	10	10	100.00
V2	alert_test	aes_alert_test	13.000s	68.993us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	5.000s	160.958us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	5.000s	160.958us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	2.000s	68.230us	5	5	100.00
		aes_csr_rw	4.000s	65.112us	20	20	100.00
		aes_csr_aliasing	4.000s	188.636us	5	5	100.00
		aes_same_csr_outstanding	23.000s	117.653us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	2.000s	68.230us	5	5	100.00
		aes_csr_rw	4.000s	65.112us	20	20	100.00
		aes_csr_aliasing	4.000s	188.636us	5	5	100.00
		aes_same_csr_outstanding	23.000s	117.653us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	11.000s	129.704us	50	50	100.00
V2S	fault_inject	aes_fi	16.000s	173.104us	50	50	100.00
		aes_control_fi			0	300	0.00
		aes_cipher_fi	16.000s	99.162us	350	350	100.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	86.772us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	86.772us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	86.772us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	86.772us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	121.552us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	5.000s	702.614us	5	5	100.00
		aes_tl_intg_err	4.000s	208.754us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	4.000s	208.754us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	15.000s	173.633us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	86.772us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	11.000s	94.633us	50	50	100.00
		aes_stress	11.000s	96.111us	50	50	100.00
		aes_alert_reset	15.000s	173.633us	50	50	100.00
		aes_core_fi	17.000s	138.927us	70	70	100.00
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	86.772us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	11.000s	95.927us	50	50	100.00
		aes_stress	11.000s	96.111us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	11.000s	96.111us	50	50	100.00
		aes_sideload	15.000s	101.692us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	11.000s	95.927us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	11.000s	95.927us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	11.000s	95.927us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	11.000s	95.927us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	11.000s	95.927us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	11.000s	96.111us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	11.000s	96.111us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	16.000s	173.104us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	16.000s	173.104us	50	50	100.00
		aes_control_fi			0	300	0.00
		aes_cipher_fi	16.000s	99.162us	350	350	100.00
		aes_ctr_fi	14.000s	123.574us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	16.000s	173.104us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	16.000s	173.104us	50	50	100.00
		aes_control_fi			0	300	0.00
		aes_cipher_fi	16.000s	99.162us	350	350	100.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	16.000s	99.162us	350	350	100.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	16.000s	173.104us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	16.000s	173.104us	50	50	100.00
		aes_control_fi			0	300	0.00
		aes_ctr_fi	14.000s	123.574us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	16.000s	173.104us	50	50	100.00
		aes_control_fi			0	300	0.00
		aes_cipher_fi	16.000s	99.162us	350	350	100.00
		aes_ctr_fi	14.000s	123.574us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	15.000s	173.633us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	16.000s	173.104us	50	50	100.00
		aes_control_fi			0	300	0.00
		aes_cipher_fi	16.000s	99.162us	350	350	100.00
		aes_ctr_fi	14.000s	123.574us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	16.000s	173.104us	50	50	100.00
		aes_control_fi			0	300	0.00
		aes_cipher_fi	16.000s	99.162us	350	350	100.00
		aes_ctr_fi	14.000s	123.574us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	16.000s	173.104us	50	50	100.00
		aes_control_fi			0	300	0.00
		aes_ctr_fi	14.000s	123.574us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	16.000s	173.104us	50	50	100.00
		aes_control_fi			0	300	0.00
		aes_cipher_fi	16.000s	99.162us	350	350	100.00
V2S		TOTAL			685	985	69.54
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	12.000s	661.648us	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1292	1602	80.65

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	10	90.91
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
91.56	92.04	84.79	94.18	86.66	97.64	86.67	98.47	76.88

Failure Buckets

• Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 300 failures:
  • Test aes_control_fi has 300 failures.

    • 0.aes_control_fi.25446945129089928198598003142800930246967241721865997696802052747230927258233
      Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_control_fi/latest/run.log

        Job ID: smart:0098a2ae-b255-4cee-9dc5-5772f2f471f0
      

    • 1.aes_control_fi.38974230615719366169222236527566789640629141369794503148030923751999308360783
      Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_control_fi/latest/run.log

        Job ID: smart:1fe41d61-8430-4771-af3a-3e3f01443e1e
      

    • ... and 298 more failures.

• UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 10 failures:
  • Test aes_stress_all_with_rand_reset has 10 failures.

    • 0.aes_stress_all_with_rand_reset.54039592658344415219635824513782623725836514372578842697737972684743887915294
      Line 593, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 661648139 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
        UVM_INFO @ 661648139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.aes_stress_all_with_rand_reset.115399732020255429961486712087569970558085719747076380040720820247879310565848
      Line 593, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 661648139 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
        UVM_INFO @ 661648139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 8 more failures.

Past Results

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