AON_TIMER Simulation Results

Tuesday May 16 2023 07:02:31 UTC

GitHub Revision: 50278df8b

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 1341560578

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke aon_timer_smoke 1.490s 579.480us 50 50 100.00
V1 csr_hw_reset aon_timer_csr_hw_reset 2.080s 1.067ms 5 5 100.00
V1 csr_rw aon_timer_csr_rw 1.290s 424.573us 20 20 100.00
V1 csr_bit_bash aon_timer_csr_bit_bash 8.790s 9.519ms 5 5 100.00
V1 csr_aliasing aon_timer_csr_aliasing 1.480s 562.000us 5 5 100.00
V1 csr_mem_rw_with_rand_reset aon_timer_csr_mem_rw_with_rand_reset 1.390s 552.928us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr aon_timer_csr_rw 1.290s 424.573us 20 20 100.00
aon_timer_csr_aliasing 1.480s 562.000us 5 5 100.00
V1 mem_walk aon_timer_mem_walk 1.120s 394.117us 5 5 100.00
V1 mem_partial_access aon_timer_mem_partial_access 1.280s 488.323us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 prescaler aon_timer_prescaler 1.392m 48.788ms 50 50 100.00
V2 jump aon_timer_jump 1.400s 619.276us 50 50 100.00
V2 stress_all aon_timer_stress_all 10.588m 376.815ms 49 50 98.00
V2 intr_test aon_timer_intr_test 1.270s 439.996us 50 50 100.00
V2 tl_d_oob_addr_access aon_timer_tl_errors 2.940s 535.120us 20 20 100.00
V2 tl_d_illegal_access aon_timer_tl_errors 2.940s 535.120us 20 20 100.00
V2 tl_d_outstanding_access aon_timer_csr_hw_reset 2.080s 1.067ms 5 5 100.00
aon_timer_csr_rw 1.290s 424.573us 20 20 100.00
aon_timer_csr_aliasing 1.480s 562.000us 5 5 100.00
aon_timer_same_csr_outstanding 5.640s 2.323ms 20 20 100.00
V2 tl_d_partial_access aon_timer_csr_hw_reset 2.080s 1.067ms 5 5 100.00
aon_timer_csr_rw 1.290s 424.573us 20 20 100.00
aon_timer_csr_aliasing 1.480s 562.000us 5 5 100.00
aon_timer_same_csr_outstanding 5.640s 2.323ms 20 20 100.00
V2 TOTAL 239 240 99.58
V2S tl_intg_err aon_timer_sec_cm 14.820s 8.212ms 5 5 100.00
aon_timer_tl_intg_err 13.580s 7.813ms 20 20 100.00
V2S sec_cm_bus_integrity aon_timer_tl_intg_err 13.580s 7.813ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset aon_timer_stress_all_with_rand_reset 13.540m 289.838ms 49 50 98.00
V3 TOTAL 49 50 98.00
TOTAL 428 430 99.53

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 6 6 5 83.33
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.50 99.82 94.68 100.00 -- 99.35 100.00 97.16

Failure Buckets

Past Results