AON_TIMER Simulation Results

Thursday April 18 2024 19:02:27 UTC

GitHub Revision: `d3942ca074`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 25859338206198790995583629940734127463564215244480240139741775999763579929205

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.410s	572.110us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.320s	1.242ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.500s	556.274us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	33.690s	13.658ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.760s	642.861us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.580s	554.891us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.500s	556.274us	20	20	100.00
		aon_timer_csr_aliasing	1.760s	642.861us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.270s	493.820us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	0.960s	295.928us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.341m	53.836ms	50	50	100.00
V2	jump	aon_timer_jump	1.430s	586.673us	50	50	100.00
V2	stress_all	aon_timer_stress_all	10.860m	403.911ms	48	50	96.00
V2	intr_test	aon_timer_intr_test	1.340s	504.496us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.780s	909.039us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.780s	909.039us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.320s	1.242ms	5	5	100.00
		aon_timer_csr_rw	1.500s	556.274us	20	20	100.00
		aon_timer_csr_aliasing	1.760s	642.861us	5	5	100.00
		aon_timer_same_csr_outstanding	6.820s	2.660ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.320s	1.242ms	5	5	100.00
		aon_timer_csr_rw	1.500s	556.274us	20	20	100.00
		aon_timer_csr_aliasing	1.760s	642.861us	5	5	100.00
		aon_timer_same_csr_outstanding	6.820s	2.660ms	20	20	100.00
V2		TOTAL			238	240	99.17
V2S	tl_intg_err	aon_timer_sec_cm	14.300s	8.273ms	5	5	100.00
		aon_timer_tl_intg_err	15.230s	8.384ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	15.230s	8.384ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	21.053m	567.281ms	36	50	72.00
V3		TOTAL			36	50	72.00
		TOTAL			414	430	96.28

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.98	99.25	93.67	100.00	--	98.40	99.51	67.06

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:473) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 16 failures:

Test aon_timer_stress_all_with_rand_reset has 14 failures.

2.aon_timer_stress_all_with_rand_reset.22565776959068798091668633709873483086645658360175798376476785450436886075603
Line 470, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/2.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 20380014005 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 20380014005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.aon_timer_stress_all_with_rand_reset.34205890338256895920674403743121886691841935418323144031109131974991741204910
Line 429, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/4.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 10334288185 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 10334288185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 12 more failures.

Test aon_timer_stress_all has 2 failures.

15.aon_timer_stress_all.106012066021986553211142364606791761529618446492358774478236595266292323787575
Line 268, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/15.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 26367239484 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 26367239484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

37.aon_timer_stress_all.46038448313345775592387726467438765237549349612600533932129688223080072665753
Line 298, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/37.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 202103909553 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 202103909553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---