AON_TIMER Simulation Results

Tuesday May 30 2023 07:03:17 UTC

GitHub Revision: f8b3c19a2

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 1284268927

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke aon_timer_smoke 1.540s 566.028us 50 50 100.00
V1 csr_hw_reset aon_timer_csr_hw_reset 2.390s 1.200ms 5 5 100.00
V1 csr_rw aon_timer_csr_rw 1.340s 479.535us 20 20 100.00
V1 csr_bit_bash aon_timer_csr_bit_bash 17.340s 11.512ms 5 5 100.00
V1 csr_aliasing aon_timer_csr_aliasing 1.580s 629.457us 5 5 100.00
V1 csr_mem_rw_with_rand_reset aon_timer_csr_mem_rw_with_rand_reset 1.390s 562.387us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr aon_timer_csr_rw 1.340s 479.535us 20 20 100.00
aon_timer_csr_aliasing 1.580s 629.457us 5 5 100.00
V1 mem_walk aon_timer_mem_walk 1.110s 423.993us 5 5 100.00
V1 mem_partial_access aon_timer_mem_partial_access 1.090s 287.829us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 prescaler aon_timer_prescaler 1.243m 51.283ms 50 50 100.00
V2 jump aon_timer_jump 1.470s 574.690us 50 50 100.00
V2 stress_all aon_timer_stress_all 14.928m 540.892ms 50 50 100.00
V2 intr_test aon_timer_intr_test 1.260s 470.598us 50 50 100.00
V2 tl_d_oob_addr_access aon_timer_tl_errors 2.630s 423.652us 20 20 100.00
V2 tl_d_illegal_access aon_timer_tl_errors 2.630s 423.652us 20 20 100.00
V2 tl_d_outstanding_access aon_timer_csr_hw_reset 2.390s 1.200ms 5 5 100.00
aon_timer_csr_rw 1.340s 479.535us 20 20 100.00
aon_timer_csr_aliasing 1.580s 629.457us 5 5 100.00
aon_timer_same_csr_outstanding 6.890s 2.631ms 20 20 100.00
V2 tl_d_partial_access aon_timer_csr_hw_reset 2.390s 1.200ms 5 5 100.00
aon_timer_csr_rw 1.340s 479.535us 20 20 100.00
aon_timer_csr_aliasing 1.580s 629.457us 5 5 100.00
aon_timer_same_csr_outstanding 6.890s 2.631ms 20 20 100.00
V2 TOTAL 240 240 100.00
V2S tl_intg_err aon_timer_sec_cm 13.240s 7.570ms 5 5 100.00
aon_timer_tl_intg_err 15.470s 8.518ms 20 20 100.00
V2S sec_cm_bus_integrity aon_timer_tl_intg_err 15.470s 8.518ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset aon_timer_stress_all_with_rand_reset 16.415m 182.817ms 49 50 98.00
V3 TOTAL 49 50 98.00
TOTAL 429 430 99.77

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 6 6 6 100.00
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.46 99.82 94.68 100.00 -- 99.35 100.00 96.90

Failure Buckets

Past Results