AON_TIMER Simulation Results

Monday October 14 2024 17:26:15 UTC

GitHub Revision: `12e3b8572e`

Branch: os_regression_2024_10_14

Simulator: VCS

Build randomization enabled with --build-seed 85025606402499621082521464627961092918263397067038954055071960501195381950243

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	3.060s	588.336us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	1.910s	1.057ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.270s	543.499us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	13.350s	7.019ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.020s	474.623us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.390s	533.410us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.270s	543.499us	20	20	100.00
		aon_timer_csr_aliasing	1.020s	474.623us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.050s	496.823us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.080s	472.551us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	2.604m	61.749ms	50	50	100.00
V2	jump	aon_timer_jump	3.090s	604.981us	50	50	100.00
V2	stress_all	aon_timer_stress_all	13.793m	486.773ms	48	50	96.00
V2	intr_test	aon_timer_intr_test	35.582s		40	50	80.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.570s	530.829us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.570s	530.829us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	1.910s	1.057ms	5	5	100.00
		aon_timer_csr_rw	1.270s	543.499us	20	20	100.00
		aon_timer_csr_aliasing	1.020s	474.623us	5	5	100.00
		aon_timer_same_csr_outstanding	4.070s	2.862ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	1.910s	1.057ms	5	5	100.00
		aon_timer_csr_rw	1.270s	543.499us	20	20	100.00
		aon_timer_csr_aliasing	1.020s	474.623us	5	5	100.00
		aon_timer_same_csr_outstanding	4.070s	2.862ms	20	20	100.00
V2		TOTAL			228	240	95.00
V2S	tl_intg_err	aon_timer_sec_cm	8.020s	7.844ms	5	5	100.00
		aon_timer_tl_intg_err	10.190s	8.529ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	10.190s	8.529ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	1.015m	7.620ms	48	50	96.00
V3		TOTAL			48	50	96.00
		TOTAL			416	430	96.74

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	4	66.67
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
89.49	99.32	95.61	100.00	--	98.38	99.51	44.13

Failure Buckets

Job returned non-zero exit code has 10 failures:

Test aon_timer_intr_test has 10 failures.

34.aon_timer_intr_test.69651445494447604128684395248095311501598576146749667905779246841171542729105
Log /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/34.aon_timer_intr_test/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Oct 14 20:56 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

35.aon_timer_intr_test.19257966242990858898504415499806342248035552321621616168296872488864443702296
Log /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/35.aon_timer_intr_test/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Oct 14 20:56 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

... and 8 more failures.

UVM_ERROR (cip_base_vseq.sv:471) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 4 failures:

Test aon_timer_stress_all_with_rand_reset has 2 failures.

18.aon_timer_stress_all_with_rand_reset.86751001302099208904179495423299661921628955914837481105057494803907664396675
Line 94, in log /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/18.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 824590114 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 824590114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

32.aon_timer_stress_all_with_rand_reset.62155947265341310325677048290559014130549856619846251500879945419478206406683
Line 365, in log /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/32.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 9972651103 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 9972651103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test aon_timer_stress_all has 2 failures.

19.aon_timer_stress_all.50301297958365757730643961836398423535403122248780163507222647373871173891923
Line 130, in log /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/19.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 92867777360 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 92867777360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

28.aon_timer_stress_all.75496195239590024479489994859282357045659253521477258272742074417819316718242
Line 110, in log /workspaces/repo/scratch/os_regression_2024_10_14/aon_timer-sim-vcs/28.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 71520752559 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 71520752559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---