AON_TIMER Simulation Results

Saturday February 08 2025 05:05:54 UTC

GitHub Revision: 9f20940d49

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 88344288495849993302635329522992994622996067932062874150778031027723701018040

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke aon_timer_smoke 2.870s 522.757us 50 50 100.00
V1 csr_hw_reset aon_timer_csr_hw_reset 4.100s 915.026us 5 5 100.00
V1 csr_rw aon_timer_csr_rw 2.540s 414.381us 20 20 100.00
V1 csr_bit_bash aon_timer_csr_bit_bash 1.161m 12.380ms 5 5 100.00
V1 csr_aliasing aon_timer_csr_aliasing 2.180s 411.147us 5 5 100.00
V1 csr_mem_rw_with_rand_reset aon_timer_csr_mem_rw_with_rand_reset 3.220s 560.916us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr aon_timer_csr_rw 2.540s 414.381us 20 20 100.00
aon_timer_csr_aliasing 2.180s 411.147us 5 5 100.00
V1 mem_walk aon_timer_mem_walk 2.010s 360.582us 5 5 100.00
V1 mem_partial_access aon_timer_mem_partial_access 2.460s 498.753us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 prescaler aon_timer_prescaler 2.466m 57.644ms 50 50 100.00
V2 jump aon_timer_jump 3.100s 597.180us 50 50 100.00
V2 stress_all aon_timer_stress_all 17.707m 544.221ms 47 50 94.00
V2 intr_test aon_timer_intr_test 2.530s 496.681us 50 50 100.00
V2 tl_d_oob_addr_access aon_timer_tl_errors 4.890s 567.903us 20 20 100.00
V2 tl_d_illegal_access aon_timer_tl_errors 4.890s 567.903us 20 20 100.00
V2 tl_d_outstanding_access aon_timer_csr_hw_reset 4.100s 915.026us 5 5 100.00
aon_timer_csr_rw 2.540s 414.381us 20 20 100.00
aon_timer_csr_aliasing 2.180s 411.147us 5 5 100.00
aon_timer_same_csr_outstanding 6.110s 2.263ms 20 20 100.00
V2 tl_d_partial_access aon_timer_csr_hw_reset 4.100s 915.026us 5 5 100.00
aon_timer_csr_rw 2.540s 414.381us 20 20 100.00
aon_timer_csr_aliasing 2.180s 411.147us 5 5 100.00
aon_timer_same_csr_outstanding 6.110s 2.263ms 20 20 100.00
V2 TOTAL 237 240 98.75
V2S tl_intg_err aon_timer_sec_cm 29.810s 8.046ms 5 5 100.00
aon_timer_tl_intg_err 28.080s 8.235ms 20 20 100.00
V2S sec_cm_bus_integrity aon_timer_tl_intg_err 28.080s 8.235ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset aon_timer_stress_all_with_rand_reset 19.833m 113.883ms 44 50 88.00
V3 TOTAL 44 50 88.00
TOTAL 421 430 97.91

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 6 6 5 83.33
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
89.75 99.33 93.67 100.00 -- 98.40 99.51 47.58

Failure Buckets

Past Results