9f20940d49
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | aon_timer_smoke | 2.870s | 522.757us | 50 | 50 | 100.00 |
V1 | csr_hw_reset | aon_timer_csr_hw_reset | 4.100s | 915.026us | 5 | 5 | 100.00 |
V1 | csr_rw | aon_timer_csr_rw | 2.540s | 414.381us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | aon_timer_csr_bit_bash | 1.161m | 12.380ms | 5 | 5 | 100.00 |
V1 | csr_aliasing | aon_timer_csr_aliasing | 2.180s | 411.147us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | aon_timer_csr_mem_rw_with_rand_reset | 3.220s | 560.916us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | aon_timer_csr_rw | 2.540s | 414.381us | 20 | 20 | 100.00 |
aon_timer_csr_aliasing | 2.180s | 411.147us | 5 | 5 | 100.00 | ||
V1 | mem_walk | aon_timer_mem_walk | 2.010s | 360.582us | 5 | 5 | 100.00 |
V1 | mem_partial_access | aon_timer_mem_partial_access | 2.460s | 498.753us | 5 | 5 | 100.00 |
V1 | TOTAL | 115 | 115 | 100.00 | |||
V2 | prescaler | aon_timer_prescaler | 2.466m | 57.644ms | 50 | 50 | 100.00 |
V2 | jump | aon_timer_jump | 3.100s | 597.180us | 50 | 50 | 100.00 |
V2 | stress_all | aon_timer_stress_all | 17.707m | 544.221ms | 47 | 50 | 94.00 |
V2 | intr_test | aon_timer_intr_test | 2.530s | 496.681us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | aon_timer_tl_errors | 4.890s | 567.903us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | aon_timer_tl_errors | 4.890s | 567.903us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | aon_timer_csr_hw_reset | 4.100s | 915.026us | 5 | 5 | 100.00 |
aon_timer_csr_rw | 2.540s | 414.381us | 20 | 20 | 100.00 | ||
aon_timer_csr_aliasing | 2.180s | 411.147us | 5 | 5 | 100.00 | ||
aon_timer_same_csr_outstanding | 6.110s | 2.263ms | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | aon_timer_csr_hw_reset | 4.100s | 915.026us | 5 | 5 | 100.00 |
aon_timer_csr_rw | 2.540s | 414.381us | 20 | 20 | 100.00 | ||
aon_timer_csr_aliasing | 2.180s | 411.147us | 5 | 5 | 100.00 | ||
aon_timer_same_csr_outstanding | 6.110s | 2.263ms | 20 | 20 | 100.00 | ||
V2 | TOTAL | 237 | 240 | 98.75 | |||
V2S | tl_intg_err | aon_timer_sec_cm | 29.810s | 8.046ms | 5 | 5 | 100.00 |
aon_timer_tl_intg_err | 28.080s | 8.235ms | 20 | 20 | 100.00 | ||
V2S | sec_cm_bus_integrity | aon_timer_tl_intg_err | 28.080s | 8.235ms | 20 | 20 | 100.00 |
V2S | TOTAL | 25 | 25 | 100.00 | |||
V3 | stress_all_with_rand_reset | aon_timer_stress_all_with_rand_reset | 19.833m | 113.883ms | 44 | 50 | 88.00 |
V3 | TOTAL | 44 | 50 | 88.00 | |||
TOTAL | 421 | 430 | 97.91 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 8 | 8 | 8 | 100.00 |
V2 | 6 | 6 | 5 | 83.33 |
V2S | 2 | 2 | 2 | 100.00 |
V3 | 1 | 1 | 0 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
89.75 | 99.33 | 93.67 | 100.00 | -- | 98.40 | 99.51 | 47.58 |
UVM_ERROR (cip_base_vseq.sv:467) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state
has 9 failures:
6.aon_timer_stress_all.65911906826858981489899220762841438043066116311254144971487460802192578974514
Line 130, in log /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/6.aon_timer_stress_all/latest/run.log
UVM_ERROR @ 144154796720 ps: (cip_base_vseq.sv:467) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
UVM_INFO @ 144154796720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
17.aon_timer_stress_all.77939605549646868299898499901918302558929240941474206479261895103373389374083
Line 74, in log /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/17.aon_timer_stress_all/latest/run.log
UVM_ERROR @ 1796915172 ps: (cip_base_vseq.sv:467) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
UVM_INFO @ 1796915172 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
8.aon_timer_stress_all_with_rand_reset.2276201697175506697734799613860771114797002511789730102629208654913270926305
Line 225, in log /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/8.aon_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 9812735753 ps: (cip_base_vseq.sv:467) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
UVM_INFO @ 9812735753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
20.aon_timer_stress_all_with_rand_reset.18628256765670484915085617952821752279946542628700342678389671043718358698743
Line 1605, in log /workspaces/repo/scratch/os_regression/aon_timer-sim-vcs/20.aon_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 113882509774 ps: (cip_base_vseq.sv:467) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
UVM_INFO @ 113882509774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.