ASSERT | PROPERTIES | SEQUENCES | |
Total | 378 | 0 | 10 |
Category 0 | 378 | 0 | 10 |
ASSERT | PROPERTIES | SEQUENCES | |
Total | 378 | 0 | 10 |
Severity 0 | 378 | 0 | 10 |
NUMBER | PERCENT | |
Total Number | 378 | 100.00 |
Uncovered | 0 | 0.00 |
Success | 378 | 100.00 |
Failure | 0 | 0.00 |
Incomplete | 4 | 1.06 |
Without Attempts | 0 | 0.00 |
NUMBER | PERCENT | |
Total Number | 10 | 100.00 |
Uncovered | 0 | 0.00 |
All Matches | 10 | 100.00 |
First Matches | 10 | 100.00 |
ASSERTIONS | CATEGORY | SEVERITY | ATTEMPTS | REAL SUCCESSES | FAILURES | INCOMPLETE | SRC |
tb.dut.u_lc_sync_escalate_en.gen_flops.OutputDelay_A | 0 | 0 | 3449208 | 3389077 | 0 | 743 | |
tb.dut.u_reg.u_wdog_count_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A | 0 | 0 | 3498843 | 430 | 0 | 424 | |
tb.dut.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A | 0 | 0 | 3498843 | 1362 | 0 | 424 | |
tb.dut.u_reg.u_wkup_count_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A | 0 | 0 | 3498843 | 2895 | 0 | 424 |
COVER SEQUENCES | CATEGORY | SEVERITY | ATTEMPTS | ALL MATCHES | FIRST MATCHES | INCOMPLETE | SRC |
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C | 0 | 0 | 804668115 | 445007 | 445007 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C | 0 | 0 | 804668115 | 382 | 382 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C | 0 | 0 | 804668115 | 887 | 887 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C | 0 | 0 | 804668115 | 559 | 559 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C | 0 | 0 | 804668115 | 806 | 806 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C | 0 | 0 | 804668115 | 444 | 444 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C | 0 | 0 | 804668115 | 469 | 469 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C | 0 | 0 | 804668115 | 1122 | 1122 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C | 0 | 0 | 804668115 | 1792 | 1792 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C | 0 | 0 | 804668115 | 15005 | 15005 | 360 |
COVER SEQUENCES | CATEGORY | SEVERITY | ATTEMPTS | ALL MATCHES | FIRST MATCHES | INCOMPLETE | SRC |
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C | 0 | 0 | 804668115 | 445007 | 445007 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C | 0 | 0 | 804668115 | 382 | 382 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C | 0 | 0 | 804668115 | 887 | 887 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C | 0 | 0 | 804668115 | 559 | 559 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C | 0 | 0 | 804668115 | 806 | 806 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C | 0 | 0 | 804668115 | 444 | 444 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C | 0 | 0 | 804668115 | 469 | 469 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C | 0 | 0 | 804668115 | 1122 | 1122 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C | 0 | 0 | 804668115 | 1792 | 1792 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C | 0 | 0 | 804668115 | 15005 | 15005 | 360 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |