Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	401100	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	5267700	1		T6	238		T7	1		T8	3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1399690	1		T6	66		T7	1		T8	6
values[0x0]	1995000	1		T6	90		T33	7		T1	6
values[0x1]	2274110	1		T6	105		T8	6		T33	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	176410	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	5492390	1		T6	252		T7	1		T8	4

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	25700	1		T20	514		T21	514		T27	514
valid_sources[0x01]	21470	1		T9	3		T12	3		T20	425
valid_sources[0x02]	21805	1		T20	431		T21	431		T27	431
valid_sources[0x03]	21070	1		T6	5		T53	5		T54	5
valid_sources[0x04]	24915	1		T1	2		T4	2		T20	497
valid_sources[0x05]	21940	1		T1	4		T4	4		T20	438
valid_sources[0x06]	23680	1		T1	4		T4	4		T9	3
valid_sources[0x07]	23210	1		T20	464		T21	464		T27	464
valid_sources[0x08]	22360	1		T6	4		T1	12		T4	12
valid_sources[0x09]	21750	1		T6	3		T1	3		T4	3
valid_sources[0x0a]	20320	1		T1	2		T4	2		T9	3
valid_sources[0x0b]	18720	1		T2	2		T3	2		T11	2
valid_sources[0x0c]	27450	1		T9	2		T12	2		T20	548
valid_sources[0x0d]	23005	1		T1	1		T4	1		T9	2
valid_sources[0x0e]	25425	1		T6	6		T53	6		T54	6
valid_sources[0x0f]	18665	1		T6	1		T1	1		T4	1
valid_sources[0x10]	25895	1		T9	2		T12	2		T20	517
valid_sources[0x11]	22710	1		T1	2		T4	2		T9	2
valid_sources[0x12]	22985	1		T20	458		T21	458		T27	458
valid_sources[0x13]	22955	1		T20	457		T21	457		T27	457
valid_sources[0x14]	22950	1		T20	457		T21	457		T27	457
valid_sources[0x15]	19015	1		T9	5		T12	5		T20	378
valid_sources[0x16]	22550	1		T20	450		T21	450		T27	450
valid_sources[0x17]	22790	1		T6	3		T53	3		T54	3
valid_sources[0x18]	25425	1		T20	506		T21	506		T27	506
valid_sources[0x19]	26000	1		T5	3		T10	3		T20	518
valid_sources[0x1a]	28340	1		T6	3		T9	9		T53	3
valid_sources[0x1b]	22370	1		T9	1		T12	1		T20	446
valid_sources[0x1c]	20250	1		T20	405		T21	405		T27	405
valid_sources[0x1d]	23780	1		T6	1		T5	3		T10	3
valid_sources[0x1e]	19860	1		T20	397		T21	397		T27	397
valid_sources[0x1f]	22240	1		T20	444		T21	444		T27	444
valid_sources[0x20]	23170	1		T20	463		T21	463		T27	463
valid_sources[0x21]	22055	1		T1	1		T4	1		T20	441
valid_sources[0x22]	22105	1		T20	442		T21	442		T27	442
valid_sources[0x23]	24220	1		T1	4		T4	4		T20	477
valid_sources[0x24]	23310	1		T20	465		T21	465		T27	465
valid_sources[0x25]	23525	1		T1	4		T4	4		T20	470
valid_sources[0x26]	27330	1		T6	4		T53	4		T54	4
valid_sources[0x27]	23250	1		T20	465		T21	465		T27	465
valid_sources[0x28]	23325	1		T20	466		T21	466		T27	466
valid_sources[0x29]	22260	1		T5	3		T10	3		T20	444
valid_sources[0x2a]	24100	1		T33	1		T15	1		T18	1
valid_sources[0x2b]	16260	1		T20	325		T21	325		T27	325
valid_sources[0x2c]	23660	1		T20	469		T21	469		T27	469
valid_sources[0x2d]	22355	1		T20	446		T21	446		T27	446
valid_sources[0x2e]	20135	1		T6	4		T53	4		T54	4
valid_sources[0x2f]	24140	1		T6	2		T53	2		T54	2
valid_sources[0x30]	23720	1		T6	1		T53	1		T54	1
valid_sources[0x31]	24260	1		T20	482		T21	482		T27	482
valid_sources[0x32]	19760	1		T6	8		T53	8		T54	8
valid_sources[0x33]	18990	1		T6	2		T53	2		T54	2
valid_sources[0x34]	23620	1		T6	1		T53	1		T54	1
valid_sources[0x35]	27120	1		T5	8		T10	8		T20	539
valid_sources[0x36]	22710	1		T6	3		T53	3		T54	3
valid_sources[0x37]	20940	1		T6	1		T9	1		T53	1
valid_sources[0x38]	23970	1		T20	479		T21	479		T27	479
valid_sources[0x39]	23900	1		T2	7		T3	7		T9	3
valid_sources[0x3a]	24010	1		T20	480		T21	480		T27	480
valid_sources[0x3b]	19080	1		T6	5		T1	1		T4	1
valid_sources[0x3c]	16505	1		T20	330		T21	330		T27	330
valid_sources[0x3d]	19920	1		T6	1		T53	1		T54	1
valid_sources[0x3e]	20600	1		T6	2		T53	2		T54	2
valid_sources[0x3f]	26300	1		T20	526		T21	526		T27	526
valid_sources[0x40]	20300	1		T20	406		T21	406		T27	406
valid_sources[0x41]	22880	1		T20	457		T21	457		T27	457
valid_sources[0x42]	19405	1		T20	386		T21	386		T27	386
valid_sources[0x43]	23475	1		T20	469		T21	469		T27	469
valid_sources[0x44]	17730	1		T1	2		T4	2		T5	11
valid_sources[0x45]	18180	1		T5	4		T10	4		T20	362
valid_sources[0x46]	20050	1		T20	401		T21	401		T27	401
valid_sources[0x47]	21365	1		T9	1		T12	1		T20	426
valid_sources[0x48]	23415	1		T2	3		T3	3		T11	3
valid_sources[0x49]	20775	1		T8	5		T34	5		T16	5
valid_sources[0x4a]	23035	1		T1	5		T4	5		T20	460
valid_sources[0x4b]	21640	1		T9	4		T12	4		T20	431
valid_sources[0x4c]	21490	1		T33	2		T15	2		T18	2
valid_sources[0x4d]	20250	1		T20	403		T21	403		T27	403
valid_sources[0x4e]	20295	1		T1	1		T4	1		T5	2
valid_sources[0x4f]	22080	1		T6	3		T33	1		T15	1
valid_sources[0x50]	22260	1		T6	2		T53	2		T54	2
valid_sources[0x51]	21100	1		T6	2		T1	2		T4	2
valid_sources[0x52]	25600	1		T1	10		T4	10		T20	511
valid_sources[0x53]	24105	1		T20	482		T21	482		T27	482
valid_sources[0x54]	25610	1		T9	8		T12	8		T20	509
valid_sources[0x55]	22850	1		T20	456		T21	456		T27	456
valid_sources[0x56]	22900	1		T20	458		T21	458		T27	458
valid_sources[0x57]	21795	1		T6	1		T5	8		T10	8
valid_sources[0x58]	20265	1		T33	1		T15	1		T18	1
valid_sources[0x59]	22635	1		T6	1		T53	1		T54	1
valid_sources[0x5a]	23570	1		T9	1		T12	1		T20	466
valid_sources[0x5b]	22705	1		T20	454		T21	454		T27	454
valid_sources[0x5c]	25620	1		T6	2		T33	1		T1	2
valid_sources[0x5d]	24855	1		T20	496		T21	496		T27	496
valid_sources[0x5e]	24070	1		T20	481		T21	481		T27	481
valid_sources[0x5f]	21070	1		T6	3		T9	2		T5	1
valid_sources[0x60]	24995	1		T6	1		T53	1		T54	1
valid_sources[0x61]	22015	1		T9	2		T12	2		T20	436
valid_sources[0x62]	21350	1		T33	3		T1	2		T15	3
valid_sources[0x63]	23170	1		T6	4		T9	7		T53	4
valid_sources[0x64]	25240	1		T6	2		T9	2		T53	2
valid_sources[0x65]	22695	1		T9	3		T12	3		T20	452
valid_sources[0x66]	21545	1		T6	3		T9	1		T53	3
valid_sources[0x67]	23210	1		T6	3		T53	3		T54	3
valid_sources[0x68]	21520	1		T6	1		T5	2		T10	2
valid_sources[0x69]	19605	1		T9	3		T12	3		T20	377
valid_sources[0x6a]	30245	1		T6	4		T9	5		T53	4
valid_sources[0x6b]	23470	1		T20	469		T21	469		T27	469
valid_sources[0x6c]	20310	1		T20	403		T21	403		T27	403
valid_sources[0x6d]	25720	1		T20	514		T21	514		T27	514
valid_sources[0x6e]	20810	1		T6	8		T53	8		T54	8
valid_sources[0x6f]	22850	1		T20	457		T21	457		T27	457
valid_sources[0x70]	16720	1		T6	1		T53	1		T54	1
valid_sources[0x71]	21910	1		T6	3		T9	2		T53	3
valid_sources[0x72]	25300	1		T9	2		T12	2		T20	504
valid_sources[0x73]	21660	1		T1	2		T4	2		T20	433
valid_sources[0x74]	23145	1		T20	461		T21	461		T27	461
valid_sources[0x75]	21860	1		T6	2		T33	2		T15	2
valid_sources[0x76]	21460	1		T6	2		T53	2		T54	2
valid_sources[0x77]	19850	1		T20	392		T21	392		T27	392
valid_sources[0x78]	20650	1		T1	10		T4	10		T9	5
valid_sources[0x79]	20465	1		T9	3		T12	3		T20	400
valid_sources[0x7a]	19835	1		T1	1		T4	1		T20	396
valid_sources[0x7b]	21450	1		T20	419		T21	419		T27	419
valid_sources[0x7c]	19200	1		T20	383		T21	383		T27	383
valid_sources[0x7d]	19780	1		T6	4		T9	4		T5	1
valid_sources[0x7e]	24215	1		T5	1		T10	1		T20	483
valid_sources[0x7f]	23730	1		T33	1		T15	1		T18	1
valid_sources[0x80]	22395	1		T9	2		T12	2		T20	446

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1309700

1

T6

66

T7

1

T8

3

values[0x0]

all_enables

biggest_size

1965375

1

T6

89

T33

5

T1

3

values[0x1]

all_enables

biggest_size

1992625

1

T6

83

T33

5

T1

2