AON_TIMER Simulation Results

Wednesday November 22 2023 20:02:38 UTC

GitHub Revision: 4002b28ec4

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56541452733628775295814943325285397402671097056517970046183331126493552547969

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke aon_timer_smoke 1.220s 491.168us 50 50 100.00
V1 csr_hw_reset aon_timer_csr_hw_reset 1.320s 775.863us 5 5 100.00
V1 csr_rw aon_timer_csr_rw 0.990s 418.151us 20 20 100.00
V1 csr_bit_bash aon_timer_csr_bit_bash 10.610s 6.158ms 5 5 100.00
V1 csr_aliasing aon_timer_csr_aliasing 1.150s 502.490us 5 5 100.00
V1 csr_mem_rw_with_rand_reset aon_timer_csr_mem_rw_with_rand_reset 1.100s 453.115us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr aon_timer_csr_rw 0.990s 418.151us 20 20 100.00
aon_timer_csr_aliasing 1.150s 502.490us 5 5 100.00
V1 mem_walk aon_timer_mem_walk 0.880s 397.008us 5 5 100.00
V1 mem_partial_access aon_timer_mem_partial_access 0.880s 397.008us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 prescaler aon_timer_prescaler 49.890s 53.248ms 50 50 100.00
V2 jump aon_timer_jump 1.050s 474.704us 50 50 100.00
V2 stress_all aon_timer_stress_all 5.104m 332.629ms 50 50 100.00
V2 intr_test aon_timer_intr_test 0.980s 396.151us 50 50 100.00
V2 tl_d_oob_addr_access aon_timer_tl_errors 1.590s 462.972us 20 20 100.00
V2 tl_d_illegal_access aon_timer_tl_errors 1.590s 462.972us 20 20 100.00
V2 tl_d_outstanding_access aon_timer_csr_hw_reset 1.320s 775.863us 5 5 100.00
aon_timer_csr_rw 0.990s 418.151us 20 20 100.00
aon_timer_csr_aliasing 1.150s 502.490us 5 5 100.00
aon_timer_same_csr_outstanding 2.030s 1.001ms 20 20 100.00
V2 tl_d_partial_access aon_timer_csr_hw_reset 1.320s 775.863us 5 5 100.00
aon_timer_csr_rw 0.990s 418.151us 20 20 100.00
aon_timer_csr_aliasing 1.150s 502.490us 5 5 100.00
aon_timer_same_csr_outstanding 2.030s 1.001ms 20 20 100.00
V2 TOTAL 240 240 100.00
V2S tl_intg_err aon_timer_sec_cm 4.630s 4.270ms 5 5 100.00
aon_timer_tl_intg_err 5.430s 4.649ms 20 20 100.00
V2S sec_cm_bus_integrity aon_timer_tl_intg_err 5.430s 4.649ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset aon_timer_stress_all_with_rand_reset 7.352m 96.760ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 430 430 100.00

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 6 6 6 100.00
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
94.43 99.82 95.32 100.00 -- 99.35 98.45 73.64

Past Results