Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	352767	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	4699110	1		T1	120		T2	20		T7	3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1254578	1		T1	95		T2	14		T7	6
values[0x0]	1791440	1		T1	66		T2	16		T7	2
values[0x1]	2005859	1		T1	59		T2	9		T7	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	161450	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	4890427	1		T1	148		T2	23		T7	4

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	19697	1		T5	2		T45	1		T11	1
valid_sources[0x01]	19091	1		T25	7		T10	1		T11	2
valid_sources[0x02]	18831	1		T45	2		T11	2		T12	2
valid_sources[0x03]	19216	1		T23	2		T45	1		T9	1
valid_sources[0x04]	19368	1		T9	1		T19	356		T20	1
valid_sources[0x05]	20305	1		T4	1		T23	1		T45	2
valid_sources[0x06]	20998	1		T45	2		T9	3		T11	1
valid_sources[0x07]	18402	1		T45	3		T11	4		T19	336
valid_sources[0x08]	19860	1		T10	1		T11	1		T18	1
valid_sources[0x09]	19817	1		T9	3		T10	1		T11	1
valid_sources[0x0a]	21807	1		T15	1		T10	1		T11	1
valid_sources[0x0b]	20789	1		T1	10		T11	1		T17	1
valid_sources[0x0c]	20089	1		T15	1		T19	307		T27	454
valid_sources[0x0d]	20667	1		T23	1		T25	2		T45	1
valid_sources[0x0e]	20147	1		T15	6		T9	15		T53	2
valid_sources[0x0f]	21701	1		T45	1		T9	3		T11	1
valid_sources[0x10]	19429	1		T23	1		T11	4		T19	338
valid_sources[0x11]	19486	1		T45	3		T9	3		T11	1
valid_sources[0x12]	19931	1		T23	2		T45	1		T9	1
valid_sources[0x13]	18876	1		T11	1		T144	5		T19	323
valid_sources[0x14]	19655	1		T15	1		T8	1		T23	1
valid_sources[0x15]	19422	1		T9	8		T11	3		T19	331
valid_sources[0x16]	18373	1		T1	6		T5	3		T45	1
valid_sources[0x17]	19665	1		T5	1		T45	1		T12	1
valid_sources[0x18]	20188	1		T45	1		T17	2		T19	284
valid_sources[0x19]	20349	1		T15	1		T11	1		T19	320
valid_sources[0x1a]	19858	1		T15	1		T9	2		T54	2
valid_sources[0x1b]	20036	1		T15	1		T23	1		T45	1
valid_sources[0x1c]	20301	1		T19	339		T20	4		T22	1
valid_sources[0x1d]	19389	1		T9	10		T11	1		T144	2
valid_sources[0x1e]	19073	1		T11	4		T57	3		T19	337
valid_sources[0x1f]	20491	1		T23	2		T25	1		T45	1
valid_sources[0x20]	19931	1		T15	1		T23	1		T11	2
valid_sources[0x21]	19094	1		T9	11		T10	1		T19	331
valid_sources[0x22]	19655	1		T8	1		T45	1		T11	3
valid_sources[0x23]	18560	1		T4	1		T45	1		T11	1
valid_sources[0x24]	20582	1		T45	1		T9	1		T144	1
valid_sources[0x25]	19896	1		T7	1		T9	2		T10	1
valid_sources[0x26]	18891	1		T4	1		T23	1		T45	2
valid_sources[0x27]	19338	1		T1	10		T45	1		T11	2
valid_sources[0x28]	19107	1		T23	1		T9	3		T11	2
valid_sources[0x29]	20223	1		T45	1		T9	7		T11	4
valid_sources[0x2a]	19102	1		T4	1		T10	3		T11	1
valid_sources[0x2b]	19466	1		T23	1		T9	4		T11	3
valid_sources[0x2c]	20607	1		T23	2		T45	1		T11	7
valid_sources[0x2d]	19762	1		T15	1		T25	3		T10	3
valid_sources[0x2e]	19982	1		T45	2		T19	367		T20	5
valid_sources[0x2f]	20289	1		T15	1		T23	1		T9	1
valid_sources[0x30]	19911	1		T1	1		T15	2		T23	1
valid_sources[0x31]	18718	1		T5	1		T23	1		T45	3
valid_sources[0x32]	19770	1		T5	1		T23	1		T45	1
valid_sources[0x33]	19007	1		T11	2		T56	1		T18	1
valid_sources[0x34]	19502	1		T23	1		T46	3		T11	2
valid_sources[0x35]	19005	1		T45	2		T54	1		T11	3
valid_sources[0x36]	19082	1		T25	1		T45	1		T11	4
valid_sources[0x37]	18537	1		T9	1		T19	315		T20	1
valid_sources[0x38]	19104	1		T45	2		T10	1		T11	4
valid_sources[0x39]	19057	1		T15	1		T45	1		T9	2
valid_sources[0x3a]	19545	1		T13	1		T23	2		T11	2
valid_sources[0x3b]	20002	1		T1	12		T7	1		T5	7
valid_sources[0x3c]	20896	1		T1	12		T4	1		T54	1
valid_sources[0x3d]	20897	1		T45	1		T11	1		T19	314
valid_sources[0x3e]	19805	1		T4	1		T5	10		T45	1
valid_sources[0x3f]	19863	1		T46	3		T9	9		T10	2
valid_sources[0x40]	19669	1		T23	1		T11	2		T19	317
valid_sources[0x41]	20414	1		T1	8		T9	4		T10	2
valid_sources[0x42]	20200	1		T19	334		T22	1		T27	307
valid_sources[0x43]	19380	1		T45	1		T10	1		T11	3
valid_sources[0x44]	18713	1		T1	10		T4	1		T23	2
valid_sources[0x45]	20840	1		T9	1		T11	2		T19	362
valid_sources[0x46]	19953	1		T7	1		T4	1		T23	1
valid_sources[0x47]	20195	1		T19	314		T22	3		T27	378
valid_sources[0x48]	18547	1		T4	2		T23	1		T25	1
valid_sources[0x49]	20080	1		T13	1		T45	1		T9	2
valid_sources[0x4a]	20742	1		T3	53		T45	2		T11	3
valid_sources[0x4b]	20613	1		T7	1		T45	2		T11	1
valid_sources[0x4c]	19685	1		T10	1		T11	1		T19	322
valid_sources[0x4d]	19362	1		T15	1		T4	1		T9	7
valid_sources[0x4e]	19337	1		T5	2		T45	1		T19	332
valid_sources[0x4f]	19534	1		T23	1		T10	2		T11	2
valid_sources[0x50]	19527	1		T23	2		T45	1		T9	9
valid_sources[0x51]	21024	1		T15	1		T23	1		T11	1
valid_sources[0x52]	19308	1		T4	1		T19	329		T27	341
valid_sources[0x53]	20654	1		T5	1		T25	4		T45	3
valid_sources[0x54]	19268	1		T5	3		T46	3		T11	3
valid_sources[0x55]	20926	1		T23	2		T45	1		T9	3
valid_sources[0x56]	20626	1		T45	1		T19	306		T20	6
valid_sources[0x57]	20177	1		T23	1		T11	2		T19	372
valid_sources[0x58]	19748	1		T2	10		T23	2		T45	1
valid_sources[0x59]	20795	1		T1	8		T5	1		T45	2
valid_sources[0x5a]	19491	1		T9	5		T11	2		T67	1
valid_sources[0x5b]	18905	1		T7	1		T10	1		T19	356
valid_sources[0x5c]	20286	1		T25	1		T45	1		T19	344
valid_sources[0x5d]	20351	1		T5	5		T9	3		T10	1
valid_sources[0x5e]	18856	1		T11	4		T144	4		T19	301
valid_sources[0x5f]	20161	1		T14	12		T67	2		T19	324
valid_sources[0x60]	19955	1		T4	1		T23	1		T45	3
valid_sources[0x61]	19287	1		T19	315		T22	4		T27	330
valid_sources[0x62]	18917	1		T4	2		T8	1		T54	1
valid_sources[0x63]	19076	1		T45	1		T9	8		T10	2
valid_sources[0x64]	19772	1		T5	5		T11	2		T19	316
valid_sources[0x65]	21845	1		T5	1		T45	1		T9	5
valid_sources[0x66]	20107	1		T19	318		T20	1		T22	1
valid_sources[0x67]	19119	1		T45	1		T9	1		T11	1
valid_sources[0x68]	19414	1		T45	1		T10	1		T11	1
valid_sources[0x69]	19530	1		T11	3		T19	310		T22	2
valid_sources[0x6a]	20927	1		T23	3		T9	1		T11	1
valid_sources[0x6b]	19520	1		T1	13		T4	1		T9	8
valid_sources[0x6c]	20741	1		T5	1		T9	14		T11	3
valid_sources[0x6d]	19432	1		T23	1		T45	1		T11	1
valid_sources[0x6e]	20888	1		T1	4		T45	3		T54	2
valid_sources[0x6f]	19545	1		T5	3		T45	2		T11	1
valid_sources[0x70]	19435	1		T1	12		T45	1		T11	2
valid_sources[0x71]	19891	1		T23	1		T45	2		T9	2
valid_sources[0x72]	19695	1		T4	1		T23	1		T11	2
valid_sources[0x73]	19692	1		T9	2		T10	1		T12	1
valid_sources[0x74]	19923	1		T7	2		T5	5		T45	2
valid_sources[0x75]	20114	1		T23	1		T10	1		T19	344
valid_sources[0x76]	20460	1		T4	1		T9	4		T144	4
valid_sources[0x77]	18386	1		T45	1		T11	2		T19	324
valid_sources[0x78]	19086	1		T5	1		T23	1		T45	1
valid_sources[0x79]	19093	1		T5	1		T9	3		T54	2
valid_sources[0x7a]	19689	1		T23	1		T11	1		T19	314
valid_sources[0x7b]	20265	1		T23	1		T9	3		T10	3
valid_sources[0x7c]	18783	1		T23	1		T45	3		T53	1
valid_sources[0x7d]	19891	1		T1	6		T23	1		T9	8
valid_sources[0x7e]	19569	1		T1	23		T25	5		T45	2
valid_sources[0x7f]	19287	1		T45	1		T54	1		T11	1
valid_sources[0x80]	20808	1		T15	1		T5	2		T23	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1175741

1

T1

35

T2

7

T7

2

values[0x0]

all_enables

biggest_size

1762073

1

T1

48

T2

10

T7

1

values[0x1]

all_enables

biggest_size

1761296

1

T1

37

T2

3

T3

29