Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	330817	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	4415360	1		T7	24		T8	4		T9	401

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1179651	1		T7	25		T8	6		T9	109
values[0x0]	1682323	1		T7	13		T8	5		T9	160
values[0x1]	1884203	1		T7	11		T8	1		T9	166

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	151697	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	4594480	1		T7	31		T8	4		T9	416

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	19607	1		T9	3		T2	2		T5	1
valid_sources[0x01]	18246	1		T11	8		T16	1		T26	3
valid_sources[0x02]	18200	1		T9	1		T3	1		T11	1
valid_sources[0x03]	18625	1		T9	2		T2	1		T11	1
valid_sources[0x04]	18652	1		T9	1		T4	3		T16	1
valid_sources[0x05]	17379	1		T14	1		T2	2		T5	1
valid_sources[0x06]	18629	1		T9	1		T2	3		T11	6
valid_sources[0x07]	17689	1		T9	1		T14	3		T11	2
valid_sources[0x08]	18786	1		T9	2		T3	1		T4	1
valid_sources[0x09]	17914	1		T8	1		T11	3		T5	1
valid_sources[0x0a]	18612	1		T9	1		T14	7		T2	3
valid_sources[0x0b]	18366	1		T9	4		T14	7		T2	2
valid_sources[0x0c]	19701	1		T9	5		T14	3		T11	6
valid_sources[0x0d]	18197	1		T9	3		T2	8		T11	2
valid_sources[0x0e]	19548	1		T14	2		T2	3		T3	4
valid_sources[0x0f]	18342	1		T16	2		T27	4		T47	5
valid_sources[0x10]	19060	1		T9	2		T14	3		T4	1
valid_sources[0x11]	19265	1		T9	3		T2	2		T5	1
valid_sources[0x12]	19255	1		T9	1		T1	2		T14	3
valid_sources[0x13]	20541	1		T7	6		T9	2		T1	4
valid_sources[0x14]	21701	1		T9	2		T14	1		T4	4
valid_sources[0x15]	17742	1		T2	4		T5	2		T16	1
valid_sources[0x16]	18511	1		T9	2		T14	2		T2	10
valid_sources[0x17]	17970	1		T14	2		T2	1		T11	3
valid_sources[0x18]	17910	1		T9	2		T14	1		T2	1
valid_sources[0x19]	16057	1		T9	3		T11	4		T4	1
valid_sources[0x1a]	20530	1		T9	3		T14	2		T11	1
valid_sources[0x1b]	19657	1		T9	3		T14	1		T2	6
valid_sources[0x1c]	18371	1		T9	2		T2	2		T4	2
valid_sources[0x1d]	18367	1		T9	2		T14	4		T11	1
valid_sources[0x1e]	16862	1		T9	2		T11	4		T27	2
valid_sources[0x1f]	17805	1		T9	2		T2	1		T4	2
valid_sources[0x20]	18499	1		T9	3		T14	5		T2	10
valid_sources[0x21]	18289	1		T9	1		T2	1		T11	2
valid_sources[0x22]	17767	1		T9	1		T5	2		T26	1
valid_sources[0x23]	18278	1		T9	2		T1	1		T14	1
valid_sources[0x24]	20191	1		T9	2		T14	6		T2	2
valid_sources[0x25]	19653	1		T8	1		T26	1		T47	3
valid_sources[0x26]	18967	1		T9	2		T14	1		T2	4
valid_sources[0x27]	18014	1		T9	2		T11	1		T27	4
valid_sources[0x28]	17770	1		T31	5		T4	4		T5	1
valid_sources[0x29]	17289	1		T9	1		T11	1		T4	3
valid_sources[0x2a]	18306	1		T9	1		T14	4		T2	4
valid_sources[0x2b]	18673	1		T8	1		T9	2		T2	3
valid_sources[0x2c]	20324	1		T9	4		T5	2		T16	3
valid_sources[0x2d]	17745	1		T9	2		T14	6		T5	2
valid_sources[0x2e]	19277	1		T9	3		T2	1		T4	1
valid_sources[0x2f]	18165	1		T9	2		T2	4		T3	1
valid_sources[0x30]	19291	1		T9	1		T1	1		T5	2
valid_sources[0x31]	20752	1		T16	2		T27	7		T24	2
valid_sources[0x32]	17670	1		T9	2		T14	1		T11	1
valid_sources[0x33]	16757	1		T9	3		T14	4		T11	1
valid_sources[0x34]	18286	1		T9	2		T14	3		T11	5
valid_sources[0x35]	16180	1		T2	1		T4	4		T17	12
valid_sources[0x36]	18157	1		T9	1		T2	3		T4	8
valid_sources[0x37]	19700	1		T9	1		T14	6		T2	7
valid_sources[0x38]	17827	1		T9	1		T1	2		T14	1
valid_sources[0x39]	18689	1		T9	2		T14	1		T2	1
valid_sources[0x3a]	19787	1		T9	2		T11	4		T5	3
valid_sources[0x3b]	18244	1		T1	2		T11	1		T5	1
valid_sources[0x3c]	18696	1		T9	3		T14	5		T2	1
valid_sources[0x3d]	19341	1		T8	1		T9	2		T2	1
valid_sources[0x3e]	18027	1		T9	3		T2	1		T16	2
valid_sources[0x3f]	18702	1		T9	2		T2	1		T26	2
valid_sources[0x40]	20177	1		T9	1		T14	3		T11	2
valid_sources[0x41]	19564	1		T9	4		T2	1		T26	7
valid_sources[0x42]	17835	1		T7	12		T9	1		T14	2
valid_sources[0x43]	17408	1		T9	1		T14	1		T2	1
valid_sources[0x44]	18411	1		T9	3		T3	5		T16	1
valid_sources[0x45]	18556	1		T9	1		T14	1		T2	1
valid_sources[0x46]	19329	1		T9	1		T14	4		T2	1
valid_sources[0x47]	17404	1		T14	2		T2	8		T11	4
valid_sources[0x48]	18256	1		T9	2		T1	2		T5	1
valid_sources[0x49]	17808	1		T9	2		T14	2		T2	3
valid_sources[0x4a]	17275	1		T9	1		T14	2		T11	4
valid_sources[0x4b]	17856	1		T9	4		T1	2		T2	1
valid_sources[0x4c]	19128	1		T9	1		T1	1		T14	2
valid_sources[0x4d]	17611	1		T2	3		T5	2		T16	2
valid_sources[0x4e]	18812	1		T9	4		T14	1		T5	1
valid_sources[0x4f]	19964	1		T9	4		T14	3		T16	2
valid_sources[0x50]	18975	1		T9	1		T2	7		T11	4
valid_sources[0x51]	17245	1		T9	2		T14	2		T5	2
valid_sources[0x52]	16027	1		T9	5		T11	3		T5	1
valid_sources[0x53]	18346	1		T14	9		T2	3		T16	2
valid_sources[0x54]	18719	1		T9	1		T1	2		T2	1
valid_sources[0x55]	19508	1		T9	2		T11	1		T5	5
valid_sources[0x56]	17593	1		T8	1		T9	3		T1	1
valid_sources[0x57]	19573	1		T9	1		T2	1		T11	3
valid_sources[0x58]	19176	1		T9	2		T2	1		T5	2
valid_sources[0x59]	20447	1		T2	8		T4	2		T5	1
valid_sources[0x5a]	17681	1		T9	3		T14	1		T2	5
valid_sources[0x5b]	20548	1		T9	2		T14	2		T2	4
valid_sources[0x5c]	20744	1		T9	3		T14	2		T5	1
valid_sources[0x5d]	18971	1		T9	1		T1	1		T14	5
valid_sources[0x5e]	18795	1		T9	1		T14	1		T11	7
valid_sources[0x5f]	17480	1		T9	2		T14	1		T16	4
valid_sources[0x60]	18925	1		T9	7		T2	1		T11	3
valid_sources[0x61]	18286	1		T9	3		T14	13		T2	2
valid_sources[0x62]	18638	1		T9	1		T14	2		T11	9
valid_sources[0x63]	18505	1		T9	1		T14	6		T11	1
valid_sources[0x64]	17984	1		T9	1		T14	7		T16	2
valid_sources[0x65]	19163	1		T9	1		T26	1		T27	4
valid_sources[0x66]	19526	1		T2	1		T4	2		T27	1
valid_sources[0x67]	16980	1		T9	1		T1	1		T11	6
valid_sources[0x68]	19101	1		T9	1		T2	1		T11	1
valid_sources[0x69]	17116	1		T8	1		T9	2		T14	1
valid_sources[0x6a]	18302	1		T2	9		T4	1		T5	2
valid_sources[0x6b]	18090	1		T9	1		T31	2		T14	1
valid_sources[0x6c]	17342	1		T9	1		T14	3		T4	1
valid_sources[0x6d]	17766	1		T9	1		T2	2		T11	4
valid_sources[0x6e]	18993	1		T9	1		T14	6		T11	5
valid_sources[0x6f]	17691	1		T9	5		T2	4		T26	1
valid_sources[0x70]	18048	1		T9	1		T14	8		T2	2
valid_sources[0x71]	18334	1		T9	2		T31	2		T14	6
valid_sources[0x72]	20364	1		T9	1		T14	9		T11	3
valid_sources[0x73]	19474	1		T9	2		T1	3		T14	1
valid_sources[0x74]	18262	1		T1	1		T2	1		T5	1
valid_sources[0x75]	17907	1		T9	1		T1	2		T2	3
valid_sources[0x76]	18797	1		T14	1		T4	1		T16	1
valid_sources[0x77]	17616	1		T14	1		T2	8		T11	4
valid_sources[0x78]	18976	1		T2	3		T11	4		T5	1
valid_sources[0x79]	19880	1		T1	7		T5	1		T16	2
valid_sources[0x7a]	17757	1		T14	10		T16	4		T27	1
valid_sources[0x7b]	18389	1		T9	1		T14	1		T5	1
valid_sources[0x7c]	18470	1		T9	4		T14	1		T11	4
valid_sources[0x7d]	19219	1		T9	2		T14	4		T2	2
valid_sources[0x7e]	19370	1		T1	6		T2	1		T11	2
valid_sources[0x7f]	17523	1		T11	6		T4	1		T5	1
valid_sources[0x80]	16981	1		T9	3		T2	1		T16	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1105509

1

T7

11

T8

3

T9

99

values[0x0]

all_enables

biggest_size

1654449

1

T7

8

T8

1

T9

158

values[0x1]

all_enables

biggest_size

1655402

1

T7

5

T9

144

T1

2