Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	715942805	6267088	0	0
wdog_bark_thold_rd_A	715942805	114593	0	0
wdog_bite_thold_rd_A	715942805	101175	0	0
wdog_ctrl_rd_A	715942805	101547	0	0
wdog_regwen_rd_A	715942805	116084	0	0
wkup_ctrl_rd_A	715942805	101281	0	0
wkup_thold_rd_A	715942805	115811	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715942805	6267088	0	0
T1	17252	0	0	0
T2	802206	4	0	0
T3	16843	0	0	0
T4	116624	0	0	0
T5	205826	0	0	0
T9	29035	761	0	0
T11	711586	2	0	0
T14	6957	458	0	0
T15	49679	0	0	0
T16	0	263	0	0
T26	0	558	0	0
T27	0	476	0	0
T29	0	4	0	0
T31	42094	0	0	0
T33	0	47019	0	0
T47	0	246	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715942805	114593	0	0
T1	17252	33	0	0
T2	802206	0	0	0
T3	16843	0	0	0
T4	0	44	0	0
T5	0	23	0	0
T7	116624	7	0	0
T8	35530	0	0	0
T9	29035	22	0	0
T11	711586	0	0	0
T14	6957	0	0	0
T15	49679	0	0	0
T17	0	2	0	0
T27	0	55	0	0
T31	42094	0	0	0
T33	0	2096	0	0
T45	0	5107	0	0
T67	0	3244	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715942805	101175	0	0
T1	17252	18	0	0
T2	802206	0	0	0
T3	16843	0	0	0
T4	0	24	0	0
T5	0	15	0	0
T7	116624	6	0	0
T8	35530	0	0	0
T9	29035	21	0	0
T11	711586	0	0	0
T14	6957	0	0	0
T15	49679	0	0	0
T27	0	24	0	0
T31	42094	0	0	0
T33	0	1803	0	0
T45	0	4400	0	0
T67	0	2670	0	0
T68	0	1397	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715942805	101547	0	0
T1	17252	36	0	0
T2	802206	0	0	0
T3	16843	0	0	0
T4	0	62	0	0
T5	0	9	0	0
T7	116624	11	0	0
T8	35530	0	0	0
T9	29035	14	0	0
T11	711586	0	0	0
T14	6957	0	0	0
T15	49679	0	0	0
T17	0	13	0	0
T27	0	6	0	0
T31	42094	0	0	0
T33	0	1826	0	0
T45	0	4474	0	0
T67	0	2824	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715942805	116084	0	0
T1	17252	14	0	0
T2	802206	0	0	0
T3	16843	0	0	0
T4	0	34	0	0
T5	0	13	0	0
T7	116624	5	0	0
T8	35530	0	0	0
T9	29035	21	0	0
T11	711586	0	0	0
T14	6957	0	0	0
T15	49679	0	0	0
T17	0	2	0	0
T27	0	21	0	0
T31	42094	0	0	0
T33	0	2109	0	0
T45	0	5404	0	0
T67	0	3134	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715942805	101281	0	0
T1	17252	20	0	0
T2	802206	0	0	0
T3	16843	0	0	0
T4	0	6	0	0
T5	0	19	0	0
T7	116624	11	0	0
T8	35530	0	0	0
T9	29035	23	0	0
T11	711586	0	0	0
T14	6957	0	0	0
T15	49679	0	0	0
T27	0	25	0	0
T31	42094	0	0	0
T33	0	1967	0	0
T45	0	4373	0	0
T67	0	3001	0	0
T68	0	1411	0	0

wkup_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715942805	115811	0	0
T1	17252	23	0	0
T2	802206	0	0	0
T3	16843	0	0	0
T4	0	26	0	0
T5	0	30	0	0
T7	116624	7	0	0
T8	35530	0	0	0
T9	29035	22	0	0
T11	711586	0	0	0
T14	6957	0	0	0
T15	49679	0	0	0
T17	0	1	0	0
T27	0	14	0	0
T31	42094	0	0	0
T33	0	2107	0	0
T45	0	5112	0	0
T67	0	3236	0	0