Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	381658	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	5087582	1		T7	6		T8	22		T1	232

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1356961	1		T7	6		T8	12		T1	194
values[0x0]	1938825	1		T7	3		T8	10		T1	126
values[0x1]	2173454	1		T7	3		T8	10		T1	121

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	173917	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	5295323	1		T7	6		T8	24		T1	289

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	20305	1		T2	20		T4	1		T45	2
valid_sources[0x01]	22671	1		T1	1		T18	1		T19	3
valid_sources[0x02]	21918	1		T18	1		T47	5		T5	1
valid_sources[0x03]	21962	1		T18	3		T3	1		T47	3
valid_sources[0x04]	23282	1		T1	1		T18	1		T5	12
valid_sources[0x05]	20915	1		T1	2		T17	3		T18	1
valid_sources[0x06]	20355	1		T1	8		T18	1		T47	1
valid_sources[0x07]	20456	1		T1	2		T18	2		T19	1
valid_sources[0x08]	20139	1		T1	1		T19	1		T2	10
valid_sources[0x09]	21188	1		T1	8		T14	1		T18	1
valid_sources[0x0a]	21413	1		T1	1		T48	1		T30	1
valid_sources[0x0b]	19589	1		T47	3		T11	2		T21	353
valid_sources[0x0c]	19881	1		T18	2		T19	1		T9	6
valid_sources[0x0d]	21789	1		T1	4		T2	1		T47	1
valid_sources[0x0e]	20158	1		T45	7		T11	5		T21	357
valid_sources[0x0f]	20334	1		T1	6		T18	1		T47	6
valid_sources[0x10]	20081	1		T18	1		T4	1		T5	1
valid_sources[0x11]	22369	1		T18	1		T5	4		T45	10
valid_sources[0x12]	21215	1		T19	1		T45	7		T10	3
valid_sources[0x13]	19953	1		T18	4		T3	6		T4	1
valid_sources[0x14]	19483	1		T1	5		T18	1		T5	2
valid_sources[0x15]	21729	1		T4	1		T5	5		T10	1
valid_sources[0x16]	20582	1		T8	2		T1	1		T18	1
valid_sources[0x17]	21958	1		T1	1		T17	3		T18	1
valid_sources[0x18]	21772	1		T1	3		T18	1		T4	2
valid_sources[0x19]	19660	1		T17	1		T18	2		T46	2
valid_sources[0x1a]	20891	1		T1	1		T18	2		T27	5
valid_sources[0x1b]	20719	1		T1	1		T4	1		T10	1
valid_sources[0x1c]	21414	1		T1	3		T9	4		T48	1
valid_sources[0x1d]	21663	1		T18	1		T47	1		T48	1
valid_sources[0x1e]	21952	1		T1	5		T19	2		T9	6
valid_sources[0x1f]	21885	1		T18	1		T47	2		T45	5
valid_sources[0x20]	22055	1		T1	6		T18	5		T4	1
valid_sources[0x21]	20475	1		T1	7		T18	1		T3	3
valid_sources[0x22]	21265	1		T1	4		T18	1		T4	1
valid_sources[0x23]	22790	1		T1	1		T17	2		T18	1
valid_sources[0x24]	21371	1		T1	7		T16	1		T5	4
valid_sources[0x25]	21287	1		T1	1		T19	1		T2	4
valid_sources[0x26]	21381	1		T8	3		T1	3		T19	3
valid_sources[0x27]	20990	1		T1	1		T18	1		T5	2
valid_sources[0x28]	22364	1		T1	1		T18	1		T46	2
valid_sources[0x29]	21376	1		T18	1		T19	1		T4	1
valid_sources[0x2a]	21522	1		T48	1		T11	2		T21	371
valid_sources[0x2b]	22426	1		T7	12		T1	1		T18	3
valid_sources[0x2c]	20169	1		T1	1		T18	1		T19	1
valid_sources[0x2d]	20969	1		T1	2		T18	2		T3	4
valid_sources[0x2e]	20854	1		T1	3		T18	1		T46	2
valid_sources[0x2f]	21661	1		T18	2		T3	1		T45	5
valid_sources[0x30]	20844	1		T1	3		T18	4		T47	1
valid_sources[0x31]	21427	1		T1	2		T9	3		T5	2
valid_sources[0x32]	20787	1		T19	1		T47	1		T5	1
valid_sources[0x33]	22619	1		T18	1		T19	1		T4	1
valid_sources[0x34]	21358	1		T1	1		T17	3		T18	1
valid_sources[0x35]	23064	1		T1	2		T18	1		T19	3
valid_sources[0x36]	20963	1		T47	2		T11	2		T21	356
valid_sources[0x37]	22263	1		T1	1		T18	2		T4	1
valid_sources[0x38]	20243	1		T18	2		T45	10		T10	1
valid_sources[0x39]	23278	1		T1	1		T18	1		T47	1
valid_sources[0x3a]	22722	1		T18	2		T5	1		T45	10
valid_sources[0x3b]	22660	1		T1	4		T18	1		T19	1
valid_sources[0x3c]	23167	1		T45	17		T10	1		T48	1
valid_sources[0x3d]	20799	1		T18	1		T10	1		T6	3
valid_sources[0x3e]	21774	1		T16	4		T17	2		T18	2
valid_sources[0x3f]	20602	1		T1	2		T18	1		T3	15
valid_sources[0x40]	20201	1		T4	1		T10	2		T6	1
valid_sources[0x41]	23029	1		T1	3		T15	9		T16	2
valid_sources[0x42]	20363	1		T2	1		T3	11		T4	1
valid_sources[0x43]	22893	1		T5	2		T45	9		T48	2
valid_sources[0x44]	20331	1		T1	5		T18	1		T19	1
valid_sources[0x45]	22323	1		T8	5		T18	2		T19	1
valid_sources[0x46]	21270	1		T18	1		T97	12		T4	1
valid_sources[0x47]	22382	1		T1	7		T16	1		T18	3
valid_sources[0x48]	20303	1		T47	1		T48	3		T21	352
valid_sources[0x49]	19413	1		T8	2		T14	1		T18	1
valid_sources[0x4a]	19705	1		T1	4		T18	1		T45	15
valid_sources[0x4b]	21641	1		T1	1		T17	1		T18	2
valid_sources[0x4c]	21612	1		T1	1		T2	34		T47	1
valid_sources[0x4d]	21846	1		T1	3		T18	4		T9	2
valid_sources[0x4e]	20675	1		T1	3		T14	1		T13	1
valid_sources[0x4f]	21727	1		T1	1		T4	2		T45	13
valid_sources[0x50]	23234	1		T1	2		T18	1		T19	1
valid_sources[0x51]	21330	1		T18	2		T4	1		T45	5
valid_sources[0x52]	23019	1		T19	2		T3	35		T45	1
valid_sources[0x53]	21040	1		T17	2		T18	1		T4	1
valid_sources[0x54]	21134	1		T17	1		T18	1		T9	19
valid_sources[0x55]	21014	1		T8	3		T18	1		T49	1
valid_sources[0x56]	23344	1		T1	5		T14	1		T4	2
valid_sources[0x57]	22197	1		T1	1		T18	5		T10	2
valid_sources[0x58]	21073	1		T1	11		T18	1		T19	1
valid_sources[0x59]	20702	1		T18	2		T2	34		T9	1
valid_sources[0x5a]	22314	1		T1	3		T18	1		T45	1
valid_sources[0x5b]	21549	1		T8	2		T1	3		T18	2
valid_sources[0x5c]	21389	1		T1	3		T19	1		T9	18
valid_sources[0x5d]	21533	1		T47	2		T4	1		T48	1
valid_sources[0x5e]	20881	1		T1	6		T4	1		T45	1
valid_sources[0x5f]	21381	1		T1	1		T18	1		T2	11
valid_sources[0x60]	21451	1		T18	1		T5	1		T10	1
valid_sources[0x61]	20719	1		T47	2		T45	5		T10	2
valid_sources[0x62]	21373	1		T18	3		T45	2		T48	2
valid_sources[0x63]	21992	1		T2	30		T3	18		T47	4
valid_sources[0x64]	21834	1		T18	1		T19	1		T46	2
valid_sources[0x65]	21273	1		T1	3		T17	2		T18	2
valid_sources[0x66]	23008	1		T8	1		T18	1		T46	5
valid_sources[0x67]	20891	1		T1	1		T5	2		T6	1
valid_sources[0x68]	21609	1		T1	2		T18	1		T5	2
valid_sources[0x69]	22295	1		T17	1		T18	1		T45	1
valid_sources[0x6a]	20360	1		T1	3		T46	2		T47	1
valid_sources[0x6b]	20448	1		T18	1		T19	1		T4	1
valid_sources[0x6c]	22045	1		T1	1		T17	1		T18	2
valid_sources[0x6d]	21672	1		T1	1		T5	3		T45	5
valid_sources[0x6e]	22368	1		T1	1		T47	3		T45	2
valid_sources[0x6f]	19582	1		T18	1		T19	1		T9	6
valid_sources[0x70]	21943	1		T1	1		T16	1		T18	1
valid_sources[0x71]	22251	1		T5	2		T45	1		T11	3
valid_sources[0x72]	21721	1		T44	3		T4	1		T5	1
valid_sources[0x73]	20058	1		T1	2		T18	2		T5	3
valid_sources[0x74]	20829	1		T11	1		T21	383		T22	274
valid_sources[0x75]	22658	1		T1	2		T18	2		T2	5
valid_sources[0x76]	21617	1		T1	1		T18	2		T9	20
valid_sources[0x77]	22666	1		T1	3		T17	2		T5	2
valid_sources[0x78]	20795	1		T1	3		T19	2		T47	1
valid_sources[0x79]	21041	1		T1	1		T19	1		T47	3
valid_sources[0x7a]	20681	1		T1	1		T14	1		T18	1
valid_sources[0x7b]	19594	1		T1	3		T17	1		T18	3
valid_sources[0x7c]	21278	1		T1	3		T17	2		T18	4
valid_sources[0x7d]	20852	1		T1	2		T4	1		T5	3
valid_sources[0x7e]	22537	1		T1	1		T18	2		T5	2
valid_sources[0x7f]	20456	1		T8	2		T1	3		T3	13
valid_sources[0x80]	20854	1		T18	1		T19	1		T4	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1272112

1

T7

4

T8

8

T1

66

values[0x0]

all_enables

biggest_size

1907355

1

T7

2

T8

8

T1

91

values[0x1]

all_enables

biggest_size

1908115

1

T8

6

T1

75

T17

7