Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	856123872	7256683	0	0
wdog_bark_thold_rd_A	856123872	96416	0	0
wdog_bite_thold_rd_A	856123872	84228	0	0
wdog_ctrl_rd_A	856123872	84363	0	0
wdog_regwen_rd_A	856123872	96528	0	0
wkup_ctrl_rd_A	856123872	84524	0	0
wkup_thold_rd_A	856123872	96991	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	856123872	7256683	0	0
T1	98661	8	0	0
T2	403913	3	0	0
T3	226872	2	0	0
T8	42791	1	0	0
T9	0	3	0	0
T14	9972	0	0	0
T15	47179	0	0	0
T16	3444	0	0	0
T17	116298	0	0	0
T18	24055	838	0	0
T19	54500	1	0	0
T44	0	1	0	0
T46	0	169	0	0
T47	0	212	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	856123872	96416	0	0
T2	403913	0	0	0
T3	226872	0	0	0
T4	93560	0	0	0
T9	228633	0	0	0
T18	24055	41	0	0
T19	54500	10	0	0
T24	0	4793	0	0
T44	23686	0	0	0
T46	9564	0	0	0
T47	15324	0	0	0
T53	0	12302	0	0
T97	3342	0	0	0
T98	0	2573	0	0
T100	0	2918	0	0
T101	0	8304	0	0
T102	0	8041	0	0
T103	0	16387	0	0
T104	0	8006	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	856123872	84228	0	0
T2	403913	0	0	0
T3	226872	0	0	0
T4	93560	0	0	0
T9	228633	0	0	0
T18	24055	14	0	0
T19	54500	12	0	0
T24	0	4339	0	0
T44	23686	0	0	0
T46	9564	0	0	0
T47	15324	0	0	0
T53	0	10533	0	0
T97	3342	0	0	0
T98	0	2233	0	0
T100	0	2497	0	0
T101	0	7850	0	0
T102	0	7144	0	0
T103	0	14298	0	0
T104	0	6701	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	856123872	84363	0	0
T2	403913	0	0	0
T3	226872	0	0	0
T4	93560	0	0	0
T9	228633	0	0	0
T18	24055	11	0	0
T19	54500	11	0	0
T24	0	4323	0	0
T44	23686	0	0	0
T46	9564	0	0	0
T47	15324	0	0	0
T53	0	10653	0	0
T97	3342	0	0	0
T98	0	2414	0	0
T100	0	2686	0	0
T101	0	7133	0	0
T102	0	7246	0	0
T103	0	13967	0	0
T104	0	6870	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	856123872	96528	0	0
T2	403913	0	0	0
T3	226872	0	0	0
T4	93560	0	0	0
T9	228633	0	0	0
T18	24055	48	0	0
T19	54500	5	0	0
T24	0	4962	0	0
T44	23686	0	0	0
T46	9564	0	0	0
T47	15324	0	0	0
T53	0	12365	0	0
T97	3342	0	0	0
T98	0	2515	0	0
T100	0	3062	0	0
T101	0	8218	0	0
T102	0	8605	0	0
T103	0	16214	0	0
T104	0	8023	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	856123872	84524	0	0
T2	403913	0	0	0
T3	226872	0	0	0
T4	93560	0	0	0
T9	228633	0	0	0
T18	24055	28	0	0
T19	54500	12	0	0
T24	0	4395	0	0
T44	23686	0	0	0
T46	9564	0	0	0
T47	15324	0	0	0
T53	0	10285	0	0
T97	3342	0	0	0
T98	0	1993	0	0
T100	0	2574	0	0
T101	0	7306	0	0
T102	0	6971	0	0
T103	0	14421	0	0
T104	0	7123	0	0

wkup_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	856123872	96991	0	0
T2	403913	0	0	0
T3	226872	0	0	0
T4	93560	0	0	0
T9	228633	0	0	0
T18	24055	6	0	0
T19	54500	5	0	0
T24	0	5052	0	0
T44	23686	0	0	0
T46	9564	0	0	0
T47	15324	0	0	0
T53	0	11838	0	0
T97	3342	0	0	0
T98	0	2609	0	0
T100	0	2937	0	0
T101	0	8093	0	0
T102	0	8869	0	0
T103	0	16364	0	0
T104	0	7944	0	0