Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	414033	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	5543994	1		T1	80		T6	4		T2	226

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1480161	1		T1	35		T6	5		T2	186
values[0x0]	2109915	1		T1	23		T6	1		T2	106
values[0x1]	2367951	1		T1	36		T6	4		T2	144

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	186898	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	5771129	1		T1	81		T6	4		T2	304

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	23579	1		T2	2		T4	2		T8	4
valid_sources[0x01]	22418	1		T2	3		T8	1		T9	3
valid_sources[0x02]	22814	1		T2	2		T8	4		T58	5
valid_sources[0x03]	22549	1		T2	1		T3	4		T7	2
valid_sources[0x04]	23257	1		T2	2		T58	5		T21	1
valid_sources[0x05]	23350	1		T2	1		T8	3		T54	12
valid_sources[0x06]	23002	1		T2	2		T9	2		T12	3
valid_sources[0x07]	23174	1		T2	2		T7	2		T58	3
valid_sources[0x08]	23560	1		T6	1		T2	2		T53	6
valid_sources[0x09]	23340	1		T2	2		T15	7		T52	1
valid_sources[0x0a]	23872	1		T3	1		T58	2		T9	3
valid_sources[0x0b]	22472	1		T1	19		T2	1		T58	1
valid_sources[0x0c]	22772	1		T1	29		T2	4		T3	10
valid_sources[0x0d]	23314	1		T15	5		T52	1		T8	4
valid_sources[0x0e]	23326	1		T2	2		T16	1		T4	1
valid_sources[0x0f]	22100	1		T2	2		T58	1		T9	2
valid_sources[0x10]	22268	1		T2	1		T3	1		T8	2
valid_sources[0x11]	22225	1		T2	7		T7	1		T58	1
valid_sources[0x12]	23275	1		T52	1		T4	2		T58	2
valid_sources[0x13]	22957	1		T2	1		T53	3		T4	5
valid_sources[0x14]	23656	1		T2	2		T4	1		T8	9
valid_sources[0x15]	21770	1		T2	4		T7	3		T8	3
valid_sources[0x16]	23775	1		T2	1		T7	1		T58	8
valid_sources[0x17]	22718	1		T2	2		T53	3		T8	8
valid_sources[0x18]	23007	1		T52	1		T58	1		T9	2
valid_sources[0x19]	23419	1		T6	2		T2	2		T58	3
valid_sources[0x1a]	23691	1		T2	3		T58	3		T9	4
valid_sources[0x1b]	23452	1		T2	4		T52	1		T8	1
valid_sources[0x1c]	24631	1		T6	2		T2	2		T7	1
valid_sources[0x1d]	23598	1		T3	7		T8	2		T58	2
valid_sources[0x1e]	22709	1		T2	2		T53	3		T8	6
valid_sources[0x1f]	25352	1		T2	1		T4	6		T8	6
valid_sources[0x20]	22845	1		T2	1		T7	2		T4	4
valid_sources[0x21]	21654	1		T52	1		T8	2		T56	11
valid_sources[0x22]	22990	1		T2	3		T56	1		T58	2
valid_sources[0x23]	23609	1		T2	1		T4	1		T8	1
valid_sources[0x24]	22632	1		T52	1		T4	1		T57	1
valid_sources[0x25]	22949	1		T2	1		T4	3		T8	3
valid_sources[0x26]	22960	1		T2	2		T16	2		T52	1
valid_sources[0x27]	22607	1		T2	1		T3	2		T52	1
valid_sources[0x28]	22976	1		T2	4		T4	1		T8	4
valid_sources[0x29]	24030	1		T2	2		T12	3		T25	236
valid_sources[0x2a]	22863	1		T58	2		T9	4		T19	1
valid_sources[0x2b]	22956	1		T2	2		T3	8		T4	2
valid_sources[0x2c]	24659	1		T2	1		T52	1		T8	2
valid_sources[0x2d]	23088	1		T2	4		T53	5		T5	1
valid_sources[0x2e]	22376	1		T2	4		T3	7		T7	1
valid_sources[0x2f]	22344	1		T15	3		T3	7		T58	4
valid_sources[0x30]	22887	1		T2	1		T16	1		T52	1
valid_sources[0x31]	22718	1		T2	4		T8	2		T58	6
valid_sources[0x32]	23690	1		T13	128		T16	1		T58	1
valid_sources[0x33]	22856	1		T2	1		T4	2		T8	2
valid_sources[0x34]	23617	1		T2	1		T9	2		T12	1
valid_sources[0x35]	23209	1		T2	1		T8	2		T58	2
valid_sources[0x36]	23204	1		T58	5		T9	2		T48	2
valid_sources[0x37]	23272	1		T3	2		T52	1		T58	1
valid_sources[0x38]	22875	1		T2	2		T3	2		T8	1
valid_sources[0x39]	22866	1		T3	1		T4	5		T58	3
valid_sources[0x3a]	23144	1		T2	1		T15	2		T8	2
valid_sources[0x3b]	22993	1		T2	2		T53	8		T9	1
valid_sources[0x3c]	23765	1		T2	1		T4	3		T8	1
valid_sources[0x3d]	23109	1		T3	4		T58	1		T9	1
valid_sources[0x3e]	23454	1		T2	2		T3	3		T7	4
valid_sources[0x3f]	23057	1		T4	1		T9	3		T25	185
valid_sources[0x40]	23312	1		T2	1		T58	5		T9	1
valid_sources[0x41]	23405	1		T2	1		T58	3		T9	2
valid_sources[0x42]	23111	1		T7	1		T52	1		T4	1
valid_sources[0x43]	22824	1		T2	6		T52	1		T8	2
valid_sources[0x44]	25514	1		T6	1		T58	2		T19	1
valid_sources[0x45]	23577	1		T1	6		T3	3		T52	1
valid_sources[0x46]	23938	1		T8	2		T54	6		T58	2
valid_sources[0x47]	22861	1		T2	3		T4	1		T58	1
valid_sources[0x48]	23248	1		T2	1		T7	1		T8	2
valid_sources[0x49]	22661	1		T2	3		T58	5		T5	3
valid_sources[0x4a]	22764	1		T2	2		T16	1		T17	21
valid_sources[0x4b]	23412	1		T2	2		T4	1		T56	24
valid_sources[0x4c]	24950	1		T17	9		T4	2		T8	1
valid_sources[0x4d]	23110	1		T2	3		T13	256		T52	2
valid_sources[0x4e]	22651	1		T2	2		T16	1		T4	3
valid_sources[0x4f]	23758	1		T2	1		T52	1		T58	1
valid_sources[0x50]	24152	1		T7	2		T8	13		T58	3
valid_sources[0x51]	23264	1		T2	1		T4	2		T9	3
valid_sources[0x52]	23183	1		T2	3		T58	5		T9	3
valid_sources[0x53]	23907	1		T3	2		T4	3		T9	1
valid_sources[0x54]	23870	1		T58	3		T9	2		T5	1
valid_sources[0x55]	22175	1		T1	17		T2	2		T3	2
valid_sources[0x56]	23378	1		T2	3		T13	128		T4	1
valid_sources[0x57]	21719	1		T2	1		T3	7		T52	1
valid_sources[0x58]	23903	1		T2	2		T3	1		T4	1
valid_sources[0x59]	24251	1		T2	1		T8	8		T58	2
valid_sources[0x5a]	23028	1		T2	1		T13	131		T4	1
valid_sources[0x5b]	22040	1		T2	2		T19	1		T25	217
valid_sources[0x5c]	23904	1		T2	2		T4	1		T8	7
valid_sources[0x5d]	22631	1		T2	2		T17	12		T58	3
valid_sources[0x5e]	23866	1		T2	3		T4	3		T56	12
valid_sources[0x5f]	23696	1		T2	2		T4	1		T56	5
valid_sources[0x60]	22820	1		T2	1		T52	1		T58	5
valid_sources[0x61]	22422	1		T2	4		T9	2		T25	221
valid_sources[0x62]	21765	1		T2	2		T16	1		T48	2
valid_sources[0x63]	23482	1		T2	2		T3	1		T58	4
valid_sources[0x64]	22932	1		T2	3		T8	2		T56	7
valid_sources[0x65]	23466	1		T4	3		T58	2		T9	2
valid_sources[0x66]	22130	1		T4	1		T8	2		T56	3
valid_sources[0x67]	22010	1		T5	2		T19	10		T21	2
valid_sources[0x68]	25468	1		T2	3		T8	1		T56	1
valid_sources[0x69]	24174	1		T7	1		T8	2		T58	1
valid_sources[0x6a]	23111	1		T2	2		T8	1		T56	7
valid_sources[0x6b]	23826	1		T2	1		T57	4		T9	4
valid_sources[0x6c]	22580	1		T7	2		T4	2		T8	5
valid_sources[0x6d]	24146	1		T8	9		T58	3		T9	5
valid_sources[0x6e]	24103	1		T3	4		T57	1		T8	1
valid_sources[0x6f]	24674	1		T2	2		T3	3		T8	3
valid_sources[0x70]	23061	1		T2	3		T4	1		T8	3
valid_sources[0x71]	22589	1		T2	2		T58	3		T21	4
valid_sources[0x72]	23644	1		T2	2		T3	1		T8	2
valid_sources[0x73]	24106	1		T2	1		T7	1		T53	1
valid_sources[0x74]	22498	1		T2	1		T3	3		T52	1
valid_sources[0x75]	24265	1		T2	2		T9	1		T25	204
valid_sources[0x76]	23385	1		T2	1		T9	1		T5	1
valid_sources[0x77]	23610	1		T2	2		T16	1		T8	7
valid_sources[0x78]	22843	1		T2	1		T58	5		T9	1
valid_sources[0x79]	22581	1		T2	3		T7	3		T58	1
valid_sources[0x7a]	23380	1		T2	3		T8	2		T58	1
valid_sources[0x7b]	22235	1		T2	1		T16	1		T4	11
valid_sources[0x7c]	22358	1		T2	2		T8	1		T56	26
valid_sources[0x7d]	22354	1		T2	2		T53	1		T58	8
valid_sources[0x7e]	22799	1		T2	1		T14	4		T16	1
valid_sources[0x7f]	25236	1		T2	1		T13	128		T3	5
valid_sources[0x80]	23550	1		T2	2		T3	1		T58	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1388559

1

T1

26

T6

3

T2

67

values[0x0]

all_enables

biggest_size

2077036

1

T1

23

T6

1

T2

71

values[0x1]

all_enables

biggest_size

2078399

1

T1

31

T2

88

T13

115