Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	856100197	7950450	0	0
wdog_bark_thold_rd_A	856100197	119682	0	0
wdog_bite_thold_rd_A	856100197	103889	0	0
wdog_ctrl_rd_A	856100197	107477	0	0
wdog_regwen_rd_A	856100197	121721	0	0
wkup_ctrl_rd_A	856100197	105800	0	0
wkup_thold_rd_A	856100197	120670	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	856100197	7950450	0	0
T1	14361	17	0	0
T2	768249	4	0	0
T3	127697	0	0	0
T6	16987	0	0	0
T7	17702	5	0	0
T8	0	7	0	0
T9	0	5	0	0
T10	0	87	0	0
T13	154087	0	0	0
T14	11260	0	0	0
T15	5652	0	0	0
T16	28178	0	0	0
T17	58752	2	0	0
T56	0	580	0	0
T57	0	223	0	0
T58	0	466	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	856100197	119682	0	0
T1	14361	11	0	0
T2	768249	0	0	0
T3	127697	0	0	0
T6	16987	0	0	0
T7	17702	2	0	0
T9	0	42	0	0
T13	154087	199	0	0
T14	11260	0	0	0
T15	5652	0	0	0
T16	28178	0	0	0
T17	58752	0	0	0
T40	0	1802	0	0
T52	0	5	0	0
T65	0	8092	0	0
T91	0	2893	0	0
T92	0	7991	0	0
T93	0	20685	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	856100197	103889	0	0
T1	14361	7	0	0
T2	768249	0	0	0
T3	127697	0	0	0
T6	16987	0	0	0
T7	17702	6	0	0
T9	0	42	0	0
T13	154087	206	0	0
T14	11260	0	0	0
T15	5652	0	0	0
T16	28178	0	0	0
T17	58752	0	0	0
T40	0	1442	0	0
T52	0	1	0	0
T65	0	6370	0	0
T91	0	2475	0	0
T92	0	6740	0	0
T93	0	17927	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	856100197	107477	0	0
T1	14361	15	0	0
T2	768249	0	0	0
T3	127697	0	0	0
T6	16987	0	0	0
T7	17702	4	0	0
T9	0	55	0	0
T13	154087	198	0	0
T14	11260	0	0	0
T15	5652	0	0	0
T16	28178	0	0	0
T17	58752	0	0	0
T40	0	1572	0	0
T52	0	8	0	0
T65	0	6830	0	0
T91	0	2804	0	0
T92	0	7457	0	0
T93	0	18175	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	856100197	121721	0	0
T1	14361	6	0	0
T2	768249	0	0	0
T3	127697	0	0	0
T6	16987	0	0	0
T7	17702	9	0	0
T9	0	45	0	0
T13	154087	227	0	0
T14	11260	0	0	0
T15	5652	0	0	0
T16	28178	0	0	0
T17	58752	0	0	0
T40	0	1845	0	0
T52	0	5	0	0
T65	0	7632	0	0
T91	0	2885	0	0
T92	0	8460	0	0
T93	0	20163	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	856100197	105800	0	0
T1	14361	17	0	0
T2	768249	0	0	0
T3	127697	0	0	0
T6	16987	0	0	0
T7	17702	18	0	0
T9	0	66	0	0
T13	154087	208	0	0
T14	11260	0	0	0
T15	5652	0	0	0
T16	28178	0	0	0
T17	58752	0	0	0
T40	0	1463	0	0
T52	0	12	0	0
T65	0	7210	0	0
T91	0	2740	0	0
T92	0	6959	0	0
T93	0	17625	0	0

wkup_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	856100197	120670	0	0
T1	14361	5	0	0
T2	768249	0	0	0
T3	127697	0	0	0
T6	16987	0	0	0
T7	17702	7	0	0
T9	0	32	0	0
T13	154087	219	0	0
T14	11260	0	0	0
T15	5652	0	0	0
T16	28178	0	0	0
T17	58752	0	0	0
T40	0	1800	0	0
T52	0	6	0	0
T65	0	7852	0	0
T91	0	3148	0	0
T92	0	8267	0	0
T93	0	20392	0	0