Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	572262122	7008565	0	0
wdog_bark_thold_rd_A	572262122	178378	0	0
wdog_bite_thold_rd_A	572262122	154717	0	0
wdog_ctrl_rd_A	572262122	153630	0	0
wdog_regwen_rd_A	572262122	178480	0	0
wkup_ctrl_rd_A	572262122	154232	0	0
wkup_thold_rd_A	572262122	176998	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	572262122	7008565	0	0
T1	167186	46448	0	0
T2	181558	0	0	0
T3	175378	0	0	0
T4	345329	0	0	0
T5	11670	0	0	0
T6	9682	0	0	0
T7	5675	0	0	0
T8	500577	0	0	0
T9	500331	0	0	0
T10	20279	0	0	0
T11	0	78850	0	0
T13	0	106330	0	0
T32	0	265072	0	0
T40	0	261042	0	0
T41	0	212240	0	0
T42	0	69923	0	0
T43	0	50635	0	0
T44	0	176965	0	0
T45	0	133072	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	572262122	178378	0	0
T1	167186	1837	0	0
T2	181558	0	0	0
T3	175378	0	0	0
T4	345329	0	0	0
T5	11670	0	0	0
T6	9682	0	0	0
T7	5675	0	0	0
T8	500577	0	0	0
T9	500331	0	0	0
T10	20279	0	0	0
T11	0	3524	0	0
T13	0	9179	0	0
T23	0	2390	0	0
T41	0	9019	0	0
T44	0	15085	0	0
T83	0	11226	0	0
T89	0	12764	0	0
T90	0	11106	0	0
T91	0	11094	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	572262122	154717	0	0
T1	167186	1618	0	0
T2	181558	0	0	0
T3	175378	0	0	0
T4	345329	0	0	0
T5	11670	0	0	0
T6	9682	0	0	0
T7	5675	0	0	0
T8	500577	0	0	0
T9	500331	0	0	0
T10	20279	0	0	0
T11	0	3205	0	0
T13	0	7628	0	0
T23	0	2150	0	0
T41	0	8186	0	0
T44	0	13060	0	0
T83	0	9338	0	0
T89	0	10577	0	0
T90	0	9859	0	0
T91	0	9429	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	572262122	153630	0	0
T1	167186	1814	0	0
T2	181558	0	0	0
T3	175378	0	0	0
T4	345329	0	0	0
T5	11670	0	0	0
T6	9682	0	0	0
T7	5675	0	0	0
T8	500577	0	0	0
T9	500331	0	0	0
T10	20279	0	0	0
T11	0	3118	0	0
T13	0	7595	0	0
T23	0	1913	0	0
T41	0	8171	0	0
T44	0	12640	0	0
T83	0	9377	0	0
T89	0	10440	0	0
T90	0	9708	0	0
T91	0	9088	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	572262122	178480	0	0
T1	167186	1983	0	0
T2	181558	0	0	0
T3	175378	0	0	0
T4	345329	0	0	0
T5	11670	0	0	0
T6	9682	0	0	0
T7	5675	0	0	0
T8	500577	0	0	0
T9	500331	0	0	0
T10	20279	0	0	0
T11	0	3515	0	0
T13	0	8749	0	0
T23	0	2284	0	0
T41	0	9641	0	0
T44	0	14617	0	0
T83	0	10823	0	0
T89	0	12642	0	0
T90	0	11557	0	0
T91	0	10950	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	572262122	154232	0	0
T1	167186	1585	0	0
T2	181558	0	0	0
T3	175378	0	0	0
T4	345329	0	0	0
T5	11670	0	0	0
T6	9682	0	0	0
T7	5675	0	0	0
T8	500577	0	0	0
T9	500331	0	0	0
T10	20279	0	0	0
T11	0	3061	0	0
T13	0	7594	0	0
T23	0	2071	0	0
T41	0	8224	0	0
T44	0	12907	0	0
T83	0	8981	0	0
T89	0	10719	0	0
T90	0	9789	0	0
T91	0	9632	0	0

wkup_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	572262122	176998	0	0
T1	167186	2115	0	0
T2	181558	0	0	0
T3	175378	0	0	0
T4	345329	0	0	0
T5	11670	0	0	0
T6	9682	0	0	0
T7	5675	0	0	0
T8	500577	0	0	0
T9	500331	0	0	0
T10	20279	0	0	0
T11	0	3628	0	0
T13	0	8721	0	0
T23	0	2409	0	0
T41	0	9379	0	0
T44	0	14875	0	0
T83	0	10369	0	0
T89	0	12684	0	0
T90	0	10975	0	0
T91	0	10883	0	0