Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
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Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
96.45 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv


Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 141 5 136 96.45


Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
bark_thold_cp 34 1 33 97.06 100 1 1 0
bite_thold_cp 34 1 33 97.06 100 1 1 0
pause_in_sleep_cp 2 1 1 50.00 100 1 1 2
prescale_cp 34 1 33 97.06 100 1 1 0
wdog_regwen_cp 2 0 2 100.00 100 1 1 2
wkup_cause_cp 1 0 1 100.00 100 1 1 0
wkup_thold_cp 34 1 33 97.06 100 1 1 0


Summary for Variable bark_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for bark_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
bark_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
bark[0] 23975 1 T1 10 T2 10 T3 10
bark[1] 412 1 T44 22 T37 128 T91 44
bark[2] 135 1 T40 16 T105 16 T93 27
bark[3] 286 1 T12 16 T106 16 T107 16
bark[4] 148 1 T13 21 T108 31 T109 32
bark[5] 304 1 T110 31 T50 17 T111 16
bark[6] 204 1 T8 16 T107 65 T109 16
bark[7] 295 1 T14 16 T40 22 T92 124
bark[8] 528 1 T93 66 T110 16 T72 120
bark[9] 379 1 T41 183 T95 12 T112 26
bark[10] 201 1 T113 12 T91 41 T114 13
bark[11] 325 1 T42 21 T115 12 T71 16
bark[12] 136 1 T41 16 T108 16 T116 26
bark[13] 264 1 T13 57 T117 22 T116 16
bark[14] 321 1 T91 72 T110 16 T69 13
bark[15] 654 1 T113 16 T109 46 T69 16
bark[16] 136 1 T39 59 T107 26 T110 17
bark[17] 249 1 T11 17 T39 136 T118 12
bark[18] 432 1 T11 16 T12 16 T36 116
bark[19] 285 1 T117 71 T107 21 T49 101
bark[20] 150 1 T14 50 T106 16 T116 16
bark[21] 475 1 T14 211 T44 30 T106 31
bark[22] 370 1 T45 12 T41 217 T119 17
bark[23] 209 1 T14 17 T106 17 T120 12
bark[24] 398 1 T8 16 T116 17 T121 12
bark[25] 592 1 T15 52 T44 63 T93 17
bark[26] 224 1 T8 17 T44 16 T37 16
bark[27] 715 1 T8 16 T15 132 T22 12
bark[28] 270 1 T70 12 T122 16 T90 47
bark[29] 416 1 T37 209 T40 17 T116 31
bark[30] 153 1 T113 17 T40 21 T50 16
bark[31] 285 1 T15 16 T36 16 T123 12
bark_0 2513 1 T1 4 T2 4 T3 4


Summary for Variable bite_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for bite_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
bite_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
bite[0] 24126 1 T1 9 T2 9 T3 9
bite[1] 130 1 T106 31 T42 20 T116 16
bite[2] 231 1 T116 16 T107 26 T110 17
bite[3] 551 1 T41 216 T91 17 T124 26
bite[4] 484 1 T15 36 T36 115 T123 11
bite[5] 94 1 T93 26 T110 16 T70 11
bite[6] 159 1 T44 16 T91 22 T89 17
bite[7] 474 1 T37 208 T105 16 T110 27
bite[8] 401 1 T125 11 T116 42 T49 94
bite[9] 214 1 T118 11 T92 123 T126 16
bite[10] 221 1 T116 31 T91 40 T127 16
bite[11] 489 1 T41 182 T116 26 T115 11
bite[12] 175 1 T14 49 T113 16 T110 16
bite[13] 572 1 T11 16 T13 21 T14 16
bite[14] 293 1 T40 20 T91 43 T92 56
bite[15] 174 1 T15 16 T106 17 T109 46
bite[16] 405 1 T11 17 T12 16 T44 30
bite[17] 214 1 T15 16 T40 42 T91 16
bite[18] 350 1 T39 135 T121 11 T71 60
bite[19] 71 1 T91 55 T128 16 - -
bite[20] 253 1 T44 22 T40 16 T42 119
bite[21] 237 1 T14 17 T41 16 T109 16
bite[22] 574 1 T37 143 T39 58 T22 11
bite[23] 338 1 T8 16 T45 11 T107 64
bite[24] 390 1 T108 47 T116 17 T93 65
bite[25] 143 1 T44 63 T41 16 T127 16
bite[26] 173 1 T8 17 T106 16 T110 47
bite[27] 249 1 T113 11 T72 119 T126 11
bite[28] 146 1 T8 16 T127 32 T48 70
bite[29] 237 1 T8 16 T36 16 T105 62
bite[30] 308 1 T13 57 T40 17 T120 11
bite[31] 611 1 T15 131 T49 26 T52 82
bite_0 2952 1 T1 5 T2 5 T3 5


Summary for Variable pause_in_sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for pause_in_sleep_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 36439 1 T1 14 T2 14 T3 14


Summary for Variable prescale_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for prescale_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
prescale_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
prescale[0] 805 1 T7 8 T8 31 T37 126
prescale[1] 730 1 T11 15 T12 15 T14 15
prescale[2] 606 1 T11 48 T14 29 T113 15
prescale[3] 782 1 T12 43 T13 55 T14 26
prescale[4] 398 1 T36 14 T108 38 T110 44
prescale[5] 1298 1 T8 2 T14 29 T15 239
prescale[6] 339 1 T8 15 T13 15 T14 15
prescale[7] 638 1 T36 59 T37 8 T38 21
prescale[8] 340 1 T113 21 T39 15 T40 86
prescale[9] 763 1 T8 39 T14 8 T15 15
prescale[10] 886 1 T36 15 T37 31 T40 15
prescale[11] 425 1 T6 8 T8 109 T11 15
prescale[12] 988 1 T11 35 T12 29 T14 113
prescale[13] 292 1 T15 2 T36 24 T129 8
prescale[14] 661 1 T12 15 T15 17 T37 15
prescale[15] 806 1 T8 105 T14 30 T15 2
prescale[16] 496 1 T14 70 T37 61 T130 8
prescale[17] 387 1 T8 41 T14 39 T15 2
prescale[18] 336 1 T14 2 T44 23 T92 15
prescale[19] 644 1 T8 28 T9 8 T14 2
prescale[20] 494 1 T14 102 T15 2 T36 2
prescale[21] 897 1 T14 115 T38 46 T107 31
prescale[22] 242 1 T11 15 T117 31 T108 36
prescale[23] 537 1 T10 8 T14 61 T47 8
prescale[24] 437 1 T14 64 T44 18 T37 15
prescale[25] 622 1 T14 15 T37 70 T39 2
prescale[26] 561 1 T8 15 T14 91 T38 2
prescale[27] 703 1 T8 15 T14 92 T15 15
prescale[28] 318 1 T8 48 T40 39 T131 8
prescale[29] 489 1 T8 39 T13 44 T43 8
prescale[30] 338 1 T8 2 T14 2 T37 54
prescale[31] 591 1 T13 15 T41 33 T109 34
prescale_0 17590 1 T1 14 T2 14 T3 14


Summary for Variable wdog_regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wdog_regwen_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 27829 1 T1 14 T2 6 T3 6
auto[1] 8610 1 T2 8 T3 8 T4 9


Summary for Variable wkup_cause_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for wkup_cause_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
wkup_cause_cleared 36439 1 T1 14 T2 14 T3 14


Summary for Variable wkup_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for wkup_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
wkup_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
wkup[0] 21816 1 T1 11 T2 11 T3 11
wkup[1] 315 1 T14 16 T44 16 T40 58
wkup[2] 430 1 T106 17 T37 16 T40 22
wkup[3] 479 1 T44 16 T106 63 T41 16
wkup[4] 330 1 T14 42 T113 16 T107 16
wkup[5] 444 1 T36 16 T37 16 T40 33
wkup[6] 370 1 T14 54 T15 16 T41 22
wkup[7] 419 1 T37 13 T41 16 T91 38
wkup[8] 514 1 T8 41 T12 16 T14 16
wkup[9] 344 1 T38 16 T40 23 T41 32
wkup[10] 413 1 T37 33 T41 16 T117 23
wkup[11] 347 1 T8 13 T13 21 T37 33
wkup[12] 355 1 T14 32 T36 17 T37 16
wkup[13] 400 1 T36 16 T44 16 T40 16
wkup[14] 330 1 T36 21 T37 16 T39 26
wkup[15] 467 1 T11 17 T14 32 T36 16
wkup[16] 446 1 T8 13 T14 34 T15 32
wkup[17] 423 1 T113 17 T41 71 T116 16
wkup[18] 339 1 T36 16 T44 22 T41 16
wkup[19] 584 1 T8 32 T12 16 T13 26
wkup[20] 426 1 T14 16 T39 26 T42 16
wkup[21] 386 1 T15 16 T36 16 T123 13
wkup[22] 309 1 T14 16 T15 36 T39 22
wkup[23] 551 1 T8 32 T12 16 T15 26
wkup[24] 312 1 T41 7 T91 17 T93 64
wkup[25] 389 1 T8 7 T40 32 T22 13
wkup[26] 293 1 T11 16 T37 48 T41 56
wkup[27] 356 1 T12 16 T15 26 T37 42
wkup[28] 560 1 T14 32 T36 16 T106 14
wkup[29] 458 1 T8 16 T11 25 T13 32
wkup[30] 435 1 T8 16 T15 22 T37 21
wkup[31] 242 1 T8 33 T44 16 T107 16
wkup_0 2157 1 T1 3 T2 3 T3 3

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